Datasheet

Data Sheet AD5735
Rev. C | Page 33 of 48
Gain Register
The 12-bit gain register allows the user to adjust the gain of
each channel in steps of 1 LSB. To write to the gain register of
one DAC channel, set the DREG[2:0] bits to 010 (see Table 14).
To write the same gain code to all four DAC channels at the
same time, set the DREG[2:0] bits to 011. The gain register
coding is straight binary, as shown in Table 15. The default code
in the gain register is 0xFFFF. The maximum recommended
gain trim is approximately 50% of the programmed range to
maintain accuracy (for more information, see the Digital Offset
and Gain Control section).
Offset Register
The 12-bit offset register allows the user to adjust the offset
of each channel by −2048 LSB to +2047 LSB in steps of 1 LSB.
To write to the offset register of one DAC channel, set the
DREG[2:0] bits to 100 (see Table 16). To write the same offset
code to all four DAC channels at the same time, set the DREG[2:0]
bits to 101. The offset register coding is straight binary, as shown in
Table 17. The default code in the offset register is 0x8000, which
results in zero offset programmed to the output (for more infor-
mation, see the Digital Offset and Gain Control section).
Clear Code Register
The 12-bit clear code register allows the user to set the clear
value of each channel. To configure a channel to be cleared
when the CLEAR pin is activated, set the CLR_EN bit in the
DAC control register for that channel (see Table 24). To write
to the clear code register, set the DREG[2:0] bits to 110 (see
Table 18). The default clear code is 0x0000 (for more informa-
tion, see the Asynchronous Clear section).
Table 14. Programming the Gain Register
R/
W
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0
0 Device address 0 1 0 DAC channel address Gain adjustment 1111
Table 15. Gain Register Bit Descriptions
Gain Adjustment G15 G14 G13 to G5 G4 G3 to G0
+4096 LSB 1 1 111111111 1 1111
+4095 LSB 1 1 111111111 0 1111
… … … … … 1111
1 LSB 0 0 000000000 1 1111
0 LSB 0 0 000000000 0 1111
Table 16. Programming the Offset Register
R/
W
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0
0 Device address 1 0 0 DAC channel address Offset adjustment 0000
Table 17. Offset Register Bit Descriptions
Offset Adjustment OF15 OF14 OF13 OF12 to OF5 OF4 OF3 to OF0
+2047 LSB 1 1 1 11111111 1 0000
+2046 LSB 1 1 1 11111111 0 0000
… … … … … … 0000
No Adjustment (Default) 1 0 0 00000000 0 0000
… … … … … … 0000
−2047 LSB 0 0 0 00000000 1 0000
−2048 LSB 0 0 0 00000000 0 0000
Table 18. Programming the Clear Code Register
R/
W
DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0
0 Device address 1 1 0 DAC channel address Clear code 0000