Datasheet

AD5735 Data Sheet
Rev. C | Page 12 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
POC
RESET
AV
DD
COMP
LV_A
–V
SENSE_A
+V
SENSE_A
COMP
DCDC_A
V
BOOST_A
V
OUT_A
I
OUT_A
AV
SS
COMP
LV_B
–V
SENSE_B
+V
SENSE_B
V
OUT_B
COMP
DCDC_B
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
R
SET_C
R
SET_D
REFOUT REFIN COMP
LV_D
–V
SENSE_D
+V
SENSE_D
COMP
DCDC_D
V
BOOST_D
V
OUT_D
I
OUT_D
AV
SS
COMP
LV_C
–V
SENSE_C
+V
SENSE_C
V
OUT_C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R
SET_B
R
SET_A
REFGND
REFGND
AD0
AD1
SYNC
SCLK
SDIN
SDO
DV
DD
DGND
LDAC
CLEAR
ALERT
FAULT
COMP
DCDC_C
I
OUT_C
V
BOOST_C
AV
CC
SW
C
GNDSW
C
GNDSW
D
SW
D
AV
SS
SW
A
GNDSW
A
GNDSW
B
SW
B
AGND
V
BOOST_B
I
OUT_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD5735
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NOTES
1.THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE POTENTIAL OF THE
AV
SS
PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED.
IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A
COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
0
9961-006
Figure 7. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 R
SET_B
An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the
I
OUT_B
temperature drift performance. For more information, see the External Current Setting Resistor section.
2 R
SET_A
An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the
I
OUT_A
temperature drift performance. For more information, see the External Current Setting Resistor section.
3 REFGND Ground Reference Point for Internal Reference.
4 REFGND Ground Reference Point for Internal Reference.
5 AD0 Address Decode for the Device Under Test (DUT) on the Board.
6 AD1
Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using
PEC, see the Packet Error Checking section.
7
SYNC
Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked
into the input shift register on the falling edge of SCLK.
8 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface
operates at clock speeds of up to 30 MHz.
9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
10 SDO Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5).
11 DV
DD
Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V.
12 DGND Digital Ground.
13
LDAC
Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs.
When LDAC
is tied permanently low, the addressed DAC data register is updated on the rising edge of
SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output
is updated only on the falling edge of LDAC
(see Figure 3). Using this mode, all analog outputs can be
updated simultaneously. The LDAC
pin must not be left unconnected.