Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC with Dynamic Power Control AD5735 Data Sheet FEATURES On-chip dynamic power control minimizes package power dissipation in current mode. This reduced power dissipation is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation.
AD5735 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Registers ........................................................................ 34 Applications ....................................................................................... 1 Readback Operation .................................................................. 37 General Description ..........................................................
Data Sheet AD5735 DETAILED FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AVSS –15V DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO AGND SWA VBOOST_A POWER-ON RESET DC-TO-DC CONVERTER DYNAMIC POWER CONTROL INPUT SHIFT REGISTER AND CONTROL FAULT STATUS REGISTER ALERT AVDD +15V 12 DAC DATA REG A + DAC INPUT REG A 12 7.4V TO 29.
AD5735 Data Sheet SPECIFICATIONS AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Data Sheet Parameter 1 ACCURACY, CURRENT OUTPUT (EXTERNAL RSET) Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 DC Crosstalk ACCURACY, CURRENT OUTPUT (INTERNAL RSET) Total Unadjusted Error (TUE) 3, 4 TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error3, 4 Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error3, 4 Full-Sca
AD5735 Parameter 1 DC-TO-DC CONVERTER Switch Switch On Resistance Switch Leakage Current Peak Current Limit Oscillator Oscillator Frequency Maximum Duty Cycle DIGITAL INPUTS2 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS2 SDO, ALERT Pins Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance FAULT Pin Output Low Voltage, VOL Data Sheet Min Typ Max 0.425 10 0.8 11.5 13 14.5 AISS 2 0.8 +1 2.6 0.
Data Sheet AD5735 AC PERFORMANCE CHARACTERISTICS AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 2 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 DYNAMIC PERFORMANCE, VOLTAGE OUTPUT Output Voltage Settling Time Min Typ Max 11 Test Conditions/Comments 5 V step to ±0.
AD5735 Data Sheet TIMING CHARACTERISTICS AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Data Sheet AD5735 Timing Diagrams t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN t19 MSB LSB t10 t10 t9 LDAC t17 t12 t11 VOUT_x LDAC = 0 t12 t16 VOUT_x t13 CLEAR t14 VOUT_x 09961-002 t18 RESET Figure 3. Serial Interface Timing Diagram SCLK 1 1 24 24 t6 SYNC MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION MSB SDO LSB UNDEFINED t15 Figure 4. Readback Timing Diagram Rev.
AD5735 Data Sheet LSB 1 MSB 16 2 SCLK SDO R/W DUT_ AD1 DUT_ AD0 SDO DISABLED X X X D15 D14 D1 D0 SDO_ ENAB STATUS STATUS STATUS STATUS Figure 5. Status Readback During Write, Timing Diagram 200µA TO OUTPUT PIN IOL VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH Figure 6. Load Circuit for SDO Timing Diagrams Rev.
Data Sheet AD5735 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
AD5735 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RSET_C RSET_D REFOUT REFIN COMPLV_D –VSENSE_D +VSENSE_D COMPDCDC_D VBOOST_D VOUT_D IOUT_D AVSS COMPLV_C –VSENSE_C +VSENSE_C VOUT_C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD5735 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COMPDCDC_C IOUT_C VBOOST_C AVCC SWC GNDSWC GNDSWD SWD AVSS SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B NOTES 1.
Data Sheet Pin No. 14 Mnemonic CLEAR 15 ALERT 16 FAULT 17 POC 18 19 20 RESET AVDD COMPLV_A 21 −VSENSE_A 22 +VSENSE_A 23 COMPDCDC_A 24 VBOOST_A 25 26 27 28 VOUT_A IOUT_A AVSS COMPLV_B 29 −VSENSE_B 30 +VSENSE_B 31 32 VOUT_B COMPDCDC_B 33 34 IOUT_B VBOOST_B 35 36 AGND SWB 37 38 39 GNDSWB GNDSWA SWA 40 41 AVSS SWD 42 GNDSWD AD5735 Description Active High, Edge Sensitive Input.
AD5735 Data Sheet Pin No. 43 44 Mnemonic GNDSWC SWC 45 46 AVCC VBOOST_C 47 48 IOUT_C COMPDCDC_C 49 50 VOUT_C +VSENSE_C 51 −VSENSE_C 52 COMPLV_C 53 54 55 56 AVSS IOUT_D VOUT_D VBOOST_D 57 COMPDCDC_D 58 +VSENSE_D 59 −VSENSE_D 60 COMPLV_D 61 62 REFIN REFOUT 63 RSET_D 64 RSET_C EPAD Description Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Switching Output for Channel C DC-to-DC Circuitry.
Data Sheet AD5735 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUTS 0.008 0.008 AVDD = +15V AVSS = –15V TA = 25°C 0.006 0.006 0.004 INL ERROR (%FSR) 0.002 0 –0.002 0.002 0 –0.002 AVDD = +15V AVSS = –15V OUTPUT UNLOADED –0.004 ±10V RANGE ±12V RANGE –0.004 –0.006 ±10V RANGE WITH DC-TO-DC CONVERTER 0 1000 2000 3000 4000 CODE –0.008 –40 09961-208 –0.006 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 8. Integral Nonlinearity Error vs. DAC Code Figure 11.
AD5735 Data Sheet 0.09 0.06 0.08 0.07 +5V RANGE ±10V RANGE ±12V RANGE 0.04 GAIN ERROR (%FSR) FULL-SCALE ERROR (%FSR) 0.05 0.03 AV DD = +15V AV SS = –15V OUTPUT UNLOADED 0.02 0.01 0.06 +5V RANGE ±10V RANGE ±12V RANGE AV DD = +15V AV SS = –15V OUTPUT UNLOADED 0.05 0.04 0.03 0.02 0.01 0 0 0 20 40 60 80 100 TEMPERATURE (°C) –0.02 –40 09961-132 –20 –20 40 20 0 60 80 100 80 100 TEMPERATURE (°C) Figure 14. Full-Scale Error vs. Temperature 09961-135 –0.01 –0.01 –40 Figure 17.
Data Sheet AD5735 1.0 12 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C OUTPUT UNLOADED 0.8 ALL RANGES TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V AVSS = –10.8V FOR AVDD < +10.8V 0.4 0.2 OUTPUT VOLTAGE (V) DNL ERROR (LSB) 0.6 8 MAX DNL 0 MIN DNL –0.2 –0.4 –0.6 4 0 –4 –8 5 10 15 20 SUPPLY (V) 30 25 –12 –5 09961-220 –1.0 10 15 Figure 23. Full-Scale Positive Step 0.020 12 0V TO 5V RANGE TA = 25°C AV SS = –26.4V FOR AV DD > +26.4V AV SS = –10.8V FOR AV DD < +10.8V 0.015 0.
AD5735 Data Sheet 15 60 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C OUTPUT UNLOADED 10 40 20 0 0 –5 –20 –40 –60 POC = 1 POC = 0 –80 AV DD = +15V AV SS = –15V ±10V RANGE TA = 25°C INT_ENABLE = 1 –100 –10 –120 0 1 2 4 3 5 6 7 8 9 10 TIME (s) –140 09961-040 –15 0 AV DD = +15V AV SS = –15V 8 10 0 ±10V RANGE OUTPUT UNLOADED TA = 25°C VOUT_X PSRR (dB) –20 100 0 –100 –200 AV DD = +15V VBOOST = +15V AV SS = –15V TA = 25°C –40 –60 –80 –300 0 1 2 3 4 5 6 7 8
Data Sheet AD5735 CURRENT OUTPUTS 0.008 0.008 4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL RSET 4mA TO 20mA, EXTERNAL RSET 0.006 0.006 INL ERROR (%FSR) 0.002 0 –0.002 0.002 0 –0.002 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL AVDD = +15V AVSS = –15V/0V –0.004 AVDD = +15V AVSS = –15V TA = 25°C –0.006 –0.
AD5735 Data Sheet 0.008 0.025 MAX INL 0.006 0.015 0.005 0 –0.005 AV DD = +15V AV SS = –15V –0.010 0.004 INL ERROR (%FSR) 0.010 4mA TO 20mA RANGE TA = 25°C AVSS = –26.4V FOR AVDD > +26.4V AVSS = –10.8V FOR AVDD < +10.8V 0.002 0 –0.002 –0.015 –0.004 –0.025 –40 –20 0 60 40 20 TEMPERATURE (°C) 80 100 –0.006 MIN INL 5 10 15 20 25 30 SUPPLY (V) 09961-240 4mA TO 20mA RANGE, INTERNAL RSET 4mA TO 20mA RANGE, EXTERNAL RSET –0.020 09961-155 TOTAL UNADJUSTED ERROR (%FSR) 0.
Data Sheet AD5735 4 MAX TUE 0 2 –0.005 0 –0.015 –0.020 –2 –4 MIN TUE –6 AV DD = +15V AV SS = –15V TA = 25°C RLOAD = 300Ω INT_ENABLE = 1 –0.025 –8 –0.030 5 10 20 15 25 –10 09961-060 –0.035 30 SUPPLY (V) 0 0.05 0.04 4mA TO 20mA RANGE TA = 25°C AV SS = –26.4V FOR AV DD > +26.4V AV SS = –10.8V FOR AV DD < +10.8V 0.01 0 MIN TUE –0.01 5 10 20 15 25 09961-061 –0.02 30 SUPPLY (V) OUTPUT CURRENT (mA) AND VBOOST_x VOLTAGE (V) TOTAL UNADJUSTED ERROR (%FSR) MAX TUE 0.
AD5735 Data Sheet 8 30 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 7 HEADROOM VOLTAGE (V) 20 AVCC = 4.5V AVCC = 5.0V AVCC = 5.5V 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 5 0 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 TIME (ms) 5 4 3 2 1 Figure 49. Output Current Settling Time with DC-to-DC Converter over AVCC (See Figure 77) 10 6 0 15 20 OUTPUT CURRENT (mA) Figure 51. DC-to-DC Converter Headroom vs.
Data Sheet AD5735 DC-TO-DC CONVERTER 80 90 20mA OUTPUT AV CC = 4.5V AV CC = 5V AV CC = 5.5V 85 70 75 70 65 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 55 50 0 4 8 12 16 20 50 40 30 24 OUTPUT CURRENT (mA) 20 –40 09961-016 60 60 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AV CC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 53. Efficiency at VBOOST_x vs.
AD5735 Data Sheet REFERENCE 5.0050 16 AV DD REFOUT TA = 25°C 12 8 6 4 2 0 5.0040 5.0035 5.0030 5.0025 5.0020 5.0015 5.0010 1.0 0.8 0.6 0.4 0.2 1.2 TIME (ms) 5.0000 –40 Figure 58. REFOUT Voltage Turn-On Transient 100 80 60 Figure 61. REFOUT Voltage vs. Temperature (When the AD5735 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV.
Data Sheet AD5735 GENERAL 450 13.4 DVDD = 5V TA = 25°C 400 13.3 350 FREQUENCY (MHz) 13.2 250 200 150 13.1 13.0 12.9 12.8 100 12.7 50 0 1 2 3 4 5 SDIN VOLTAGE (V) 12.6 –40 09961-007 0 DVDD = 5.5V –20 0 20 40 60 80 09961-020 DICC (µA) 300 100 TEMPERATURE (°C) Figure 64. DICC vs. Logic Input Voltage Figure 67. Internal Oscillator Frequency vs. Temperature 10 14.4 8 14.2 6 AIDD AISS TA = 25°C VOUT = 0V OUTPUT UNLOADED 0 14.
AD5735 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation from the best fit line through the DAC transfer function. INL is expressed in percent of full-scale range (% FSR). Typical INL vs. code plots are shown in Figure 8 and Figure 31.
Data Sheet AD5735 Digital-to-Analog Glitch Energy Digital-to-analog glitch energy is the impulse injected into the analog output when the input code in the DAC register changes state but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 25.
AD5735 Data Sheet THEORY OF OPERATION The AD5735 is a quad, precision digital-to-current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop and unipolar/bipolar voltage outputs. VBOOST_x R2 T2 A2 DAC ARCHITECTURE The DAC core architecture of the AD5735 consists of two matched DAC sections.
Data Sheet AD5735 POWER-ON STATE OF THE AD5735 On initial power-up of the AD5735, the state of the power-on reset circuit is dependent on the power-on condition (POC) pin. • • If POC = 0, both the voltage output and current output channels power up in tristate mode. If POC = 1, the voltage output channel powers up with a 30 kΩ pull-down resistor to ground, and the current output channel powers up in tristate mode.
AD5735 Data Sheet REGISTERS Table 8, Table 9, and Table 10 provide an overview of the registers for the AD5735. Table 8. Data Registers for the AD5735 Register DAC Data Registers Gain Registers Offset Registers Clear Code Registers Description The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel. The DAC data bits are D15 to D4. The four gain registers (one register per DAC channel) are used to program the gain trim on a per-channel basis.
Data Sheet AD5735 ENABLING THE OUTPUT Reprogramming the Output Range To correctly write to and set up the part from a power-on condition, use the following sequence: When changing the range of an output, the same sequence described in the Enabling the Output section should be used. It is recommended that the range be set to 0 V (zero scale or midscale) before the output is disabled.
AD5735 Data Sheet DATA REGISTERS DAC Data Register The input shift register is 24 bits wide. When PEC is enabled, the input shift register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information about PEC). When writing to a data register, the format shown in Table 11 must be used. When writing to a DAC data register, Bit D15 to Bit D4 are the DAC data bits.
Data Sheet AD5735 Gain Register DREG[2:0] bits to 100 (see Table 16). To write the same offset code to all four DAC channels at the same time, set the DREG[2:0] bits to 101. The offset register coding is straight binary, as shown in Table 17. The default code in the offset register is 0x8000, which results in zero offset programmed to the output (for more information, see the Digital Offset and Gain Control section).
AD5735 Data Sheet CONTROL REGISTERS Main Control Register When writing to a control register, the format shown in Table 19 must be used. See Table 12 for information about the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift register) to 111 and then setting the CREG[2:0] bits to select the specific control register (see Table 20). The main control register options are shown in Table 21 and Table 22.
Data Sheet AD5735 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 23 and Table 24. Table 23. Programming the DAC Control Register D15 0 1 D14 1 D13 0 D12 X1 D11 X1 D10 X1 D9 X1 D8 D7 D6 INT_ENABLE CLR_EN OUTEN D5 RSET D4 DC_DC D3 OVRNG D2 R2 D1 R1 D0 R0 X = don’t care. Table 24.
AD5735 Data Sheet Software Register The software register allows the user to perform a software reset of the part. This register is also used to set the user toggle bit, D11, in the status register and as part of the watchdog timer feature when that feature is enabled. Bit D12 in the software register can be used to ensure that communication has not been lost between the MCU and the AD5735 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC).
Data Sheet AD5735 Slew Rate Control Register This register is used to program the slew rate control for the selected DAC channel. This feature is available on both the current and voltage outputs. The slew rate control is enabled/ disabled and programmed on a per-channel basis. See Table 29 and the Digital Slew Rate Control section for more information. READBACK OPERATION Readback mode is invoked by setting the R/W bit = 1 in the serial input register write.
AD5735 Data Sheet Status Register read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation (see the Readback Operation section). The status register is a read-only register. This register contains any fault information, as a well as a ramp active bit (Bit D9) and a user toggle bit (Bit D11).
Data Sheet AD5735 DEVICE FEATURES FAULT OUTPUT The AD5735 is equipped with a FAULT pin, an active low, open-drain output that allows several AD5735 devices to be connected together to one pull-up resistor for global fault detection.
AD5735 Data Sheet ASYNCHRONOUS CLEAR ignored. If status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with PEC. CLEAR is an active high, edge sensitive input that allows the output to be cleared to a preprogrammed 12-bit code. This code is user-programmable via a per-channel 12-bit clear code register. WATCHDOG TIMER For a channel to be cleared, set the CLR_EN bit in the DAC control register for that channel.
Data Sheet AD5735 DIGITAL SLEW RATE CONTROL The digital slew rate control feature of the AD5735 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load.
AD5735 Data Sheet DC-TO-DC CONVERTERS DC-to-DC Converter VMAX Functionality The AD5735 contains four independent dc-to-dc converters. These are used to provide dynamic control of the VBOOST_x supply voltage for each channel (see Figure 71). Figure 77 shows the discrete components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry. The maximum VBOOST_x voltage is set in the dc-to-dc control register (23 V, 24.5 V, 27 V, or 29.
Data Sheet AD5735 DC-to-DC Converter External Schottky Diode Selection AICC SUPPLY REQUIREMENTS—STATIC The AD5735 requires an external Schottky diode for correct operation. Ensure that the Schottky diode is rated to handle the maximum reverse breakdown voltage expected in operation and that the maximum junction temperature of the diode is not exceeded. The average current of the diode is approximately equal to the ILOAD current.
AD5735 Data Sheet Reducing AICC Current Requirements Using Slew Rate Control Two main methods can be used to reduce the AICC current requirements. One method is to add an external compensation resistor, and the other is to use slew rate control. These methods can be used together. Using slew rate control can greatly reduce the current requirements of the AVCC supply, as shown in Figure 82. 0.8 0.5 20 0.4 16 0.3 12 0.2 8 AICC IOUT VBOOST 0.1 4 0 0 0.5 1.0 1.5 TIME (ms) 0.3 12 0.2 8 0.
Data Sheet AD5735 APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT PINS ON THE SAME TERMINAL When using a channel of the AD5735, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. The two output pins can be tied together because only the voltage output or the current output can be enabled at any one time.
AD5735 Data Sheet DRIVING INDUCTIVE LOADS MICROPROCESSOR INTERFACING When driving inductive or poorly defined loads, a capacitor may be required between the IOUT_x pin and the AGND pin to ensure stability. A 0.01 µF capacitor between IOUT_x and AGND ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5735. There is no maximum capacitance limit for the current output of the AD5735.
Data Sheet AD5735 • The power supply lines of the AD5735 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs.
AD5735 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 1 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-13-2012-C SEATING PLANE 16 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.
