Datasheet
AD5726 Data Sheet
Rev. C | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AV
DD
1
V
OUTD
2
V
OUTC
3
V
REFN
4
CLRSEL
16
CLR
15
LDAC
14
NC
13
V
REFP
5
V
OUTB
6
V
OUTA
7
CS
12
SCLK
11
SDIN
10
AV
SS
8
GND
9
NC = NO CONNECT
TOP VIEW
(Not to Scale)
AD5726
06469-005
06469-033
AV
DD
1
V
OUTD
2
V
OUTC
3
V
REFN
4
CLRSEL
20
CLR
19
LDAC
18
NC
17
NC
5
NC
6
V
REFP
7
NC
16
NC
15
CS
14
V
OUTB
8
SCLK
13
V
OUTA
9
SDIN
12
AV
SS
10
GND
11
NC = NO CONNECT
AD5726
TOP VIEW
(Not to Scale)
Figure 5. 16-Lead SSOP and 16-Lead SOIC Pin Configuration Figure 6. 20-Lead SSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
16-Lead SSOP/SOIC
20-Lead SSOP
1
1
AV
DD
Positive Analog Supply Pin. Voltage range is from 5 V to 15 V.
2
2
V
OUTD
Buffered Analog Output Voltage of DAC D.
3 3 V
OUTC
Buffered Analog Output Voltage of DAC C.
4 4 V
REFN
Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale
output. Allowable range is AV
SS
to V
REFP
− 2.5 V.
5
7
V
REFP
Positive DAC Reference Input. The voltage applied to this pin defines the full-scale
output voltage. Allowable range is AV
DD
− 2.5 V to V
REFN
+ 2.5 V.
6
8
V
OUTB
Buffered Analog Output Voltage of DAC B.
7 9 V
O U TA
Buffered Analog Output Voltage of DAC A.
8 10 AV
SS
Negative Analog Supply Pin. Voltage range is from 0 V to −15 V.
9 11 GND Ground Reference Pin.
10
12
SDIN
Serial Data Input. Data must be valid on the rising edge of SCLK. This input is ignored
when
CS
is high.
11 13 SCLK Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK.
12 14 CS
Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin
is logically OR’ed with the SCLK input and disables the serial data input when high.
13 5, 6, 15, 16, 17 NC No Internal Connection.
14
18
LDAC
Active Low, Asynchronous Load DAC Input. The data currently contained in the
serial input register is transferred out to the DAC data registers on the falling edge
of
LDAC
, independent of
CS
. Input data must remain stable while
LDAC
is low.
15 19 CLR
Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or
midscale (0x800), depending on the state of CLRSEL. The data in the serial input
register is unaffected by this control.
16 20 CLRSEL Determines the action of
CLR
. If high, a clear command sets the internal DAC
registers to midscale (0x800). If low, the registers are set to zero (0x000).