Datasheet

AD5726 Data Sheet
Rev. C | Page 6 of 20
TIMING CHARACTERISTICS
AV
DD
= +15 V or +5 V, AV
SS
= −15 V or −5 V or 0 V, GND = 0 V; V
REFP
= +10 V or +2.5 V; V
REFN
= −10 V or −2.5 V or 0 V, R
LOAD
= 2 kΩ,
C
L
= 200 pF. All specifications T
MIN
to T
MAX
, unless otherwise noted.
1, 2
Table 4.
Parameter Limit at T
MIN
, T
MAX
Unit Description
t
DS
5 ns Data setup time
t
DH
5 ns Data hold time
t
CH
13 ns Clock pulse width high
t
CL
13 ns Clock pulse width low
t
CSS
13 ns Select time
t
CSH
13 ns Deselect delay
t
LD1
20 ns Load disable time
t
LD2
20 ns Load delay
t
LDW
20 ns Load pulse width
t
CLRW
20 ns Clear pulse width
1
Guaranteed by design and characterization, not production tested.
2
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Timing Diagrams
CS
SDIN
SCLK
LDAC
t
CSS
t
LD1
t
CSH
t
LD2
A1 A0 X X D11 D10 D9 D8 D4 D3 D2 D1 D0
06469-002
Figure 2. Data Load Sequence
SDIN
SCLK
V
OUT
CS
LDAC
t
DS
t
CL
t
CH
t
CSH
t
LD2
t
LDW
t
S
t
DH
±1LSB
0
6469-003
Figure 3. Data Load Timing
CLRSEL
V
OUT
CLR
t
CLRW
t
S
±1LSB
0
6469-004
Figure 4. Clear Timing