Datasheet
Data Sheet AD5724/AD5734/AD5754
Rev. F | Page 9 of 31
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06468-005
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5724/
AD5734/
AD5754
CLR
LDAC
AV
SS
NC
V
OUT
A
V
OUT
B
SYNC
NC
BIN/2sCOMP
GND
SDO
REFIN
SIG_GND
SCLK
SDIN
NC
AV
DD
V
OUT
C
V
OUT
D
SIG_GND
DAC_GND
DAC_GND
DV
CC
NC
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERMAL PERFORMANCE.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 AV
SS
Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can connect to 0 V if output ranges
are unipolar.
2, 6, 12, 13 NC No connect. Do not connect to these pins.
3 V
OUT
A Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
4 V
OUT
B Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
5 BIN/
2sCOMP
Determines the DAC coding for a bipolar output range. This pin must be hardwired to either DV
CC
or GND.
When hardwired to DV
CC
, input coding is offset binary. When hardwired to GND, input coding is twos
complement. (For unipolar output ranges, coding is always straight binary).
7
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While
SYNC
is low, data is
transferred on the falling edge of SCLK. Data is latched on the rising edge of
SYNC
.
8 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
10
LDAC
Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog outputs. When
this pin is tied permanently low, the addressed DAC register is updated on the rising edge of
SYNC
. If
LDAC
is
held high during the write cycle, the DAC input register is updated, but the output update is held off until the
falling edge of
LDAC
. In this mode, all analog outputs can be updated simultaneously on the falling edge of
LDAC
. The
LDAC
pin must not be left unconnected.
11
CLR
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable).
14 DV
CC
Digital Supply. Voltage ranges from 2.7 V to 5.5 V.
15 GND Ground Reference.
16 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
17 REFIN
External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance.
18, 19 DAC_GND Ground Reference for the Four Digital-to-Analog Converters.
20, 21 SIG_GND Ground Reference for the Four Output Amplifiers.
22 V
OUT
D Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
23 V
OUT
C Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
24 AV
DD
Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V.
Exposed
Paddle
AV
SS
This exposed paddle can be connected to the potential of the AV
SS
pin, or alternatively, it can be left electrically
unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal
performance.
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