Datasheet

AD5724/AD5734/AD5754 Data Sheet
Rev. F | Page 4 of 31
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS
3
DV
CC
= 2.7 V to 5.5 V, JEDEC compliant
Input High Voltage, V
IH
2 V
Input Low Voltage, V
IL
0.8 V
Input Current ±1 µA Per pin
Pin Capacitance
5
pF
Per pin
DIGITAL OUTPUTS (SDO)
3
Output Low Voltage, V
OL
0.4 V DV
CC
= 5 V ± 10%, sinking 200 µA
Output High Voltage, V
OH
DV
CC
− 1 V DV
CC
= 5 V ± 10%, sourcing 200 µA
Output Low Voltage, V
OL
0.4 V DV
CC
= 2.7 V to 3.6 V, sinking 200 µA
Output High Voltage, V
OH
DV
CC
− 0.5 V DV
CC
= 2.7 V to 3.6 V, sourcing 200 µA
High Impedance Leakage Current −1 +1 µA
High Impedance Output Capacitance 5 pF
POWER REQUIREMENTS
AV
DD
4.5 16.5 V
AV
SS
−4.5 −16.5 V
DV
CC
2.7
5.5
V
Power Supply Sensitivity
3
∆V
OUT
/∆ΑV
DD
−65 dB
AI
DD
2.5 mA/channel Outputs unloaded
1.75 mA/channel AV
SS
= 0 V, outputs unloaded
AI
SS
2.2 mA/channel Outputs unloaded
DI
CC
0.5 3 µA V
IH
= DV
CC
, V
IL
= GND
Power Dissipation 310 mW ±16.5 V operation, outputs unloaded
115 mW 16.5 V operation, AV
SS
= 0 V, outputs unloaded
Power-Down Currents
AI
DD
40 µA
AI
SS
40 µA
DI
CC
300 nA
1
For specified performance, maximum headroom requirement is 0.9 V.
2
INL is measured from Code 512, Code 128, and Code 32 for the AD5754, the AD5734, and the AD5724, respectively.
3
Guaranteed by characterization; not production tested.
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