Datasheet
AD5724/AD5734/AD5754 Data Sheet
Rev. F | Page 28 of 31
APPLICATIONS INFORMATION
+5 V/±5 V OPERATION
When operating from a single +5 V supply or a dual ±5 V
supply, an output range of +5 V or ±5 V is not achievable because
sufficient headroom for the output amplifier is not available. In
this situation, a reduced reference voltage can be used. For example,
a 2 V reference voltage produces an output range of +4 V or ±4 V,
and the 1 V of headroom is more than enough for full operation. A
standard value voltage reference of 2.048 V can be used to produce
output ranges of +4.096 V and ±4.096 V.
ALTERNATIVE POWER-UP SEQUENCE SUPPORT
There may be cases where it is not possible to use the
recommended power-up sequence, and in those instances an
external circuit shown in Figure 43 is recommended to be used.
The circuit shown in Figure 43 ensures that the digital block is
powered up first, prior to the analog block, by using a load
switch circuit. This circuit targets applications for which either
AV
DD
or AV
SS
or both supplies power up before DV
CC
.
Consider the following design rules when choosing the
component values for the AV
DD
delay circuit.
R1 ensures that the Q1 gate to source voltage is zero when
DV
CC
is in an open state. R1 also prevents false turn on of
Q1. However, if DV
CC
is permanently connected to the
source, R1 can be removed to conserve power.
Select Q1 (N-channel MOSFET) with a V
GS
threshold that
is much lower than the minimum operating DV
CC
and a
V
DS
rating much lower than the maximum operating AV
DD
.
C1, R2, and R3 are the main components that dictates the
delay from DV
CC
enable to AV
DD
. Adjust the values
according for the desired delay. Choose R2 and R3 values
that ensure Q2 turn on.
EQ
GS
DELAY
V
V
RRCt 1ln)||()sec(
231
where
23
3
RR
R
AVV
DD
EQ
Q2 (P-channel MOSFET) acts as a switch that allows the flow
of current from V
IN
to AV
DD
; therefore, choosing a MOSFET
with very low R
DSON
is necessary to minimize losses during
operation. Other parameters such as maximum V
DS
rating,
maximum drain to source current rating, V
GS
threshold
voltage, and maximum gate to source voltage rating must
also be taken into consideration when choosing Q2.
C1
V
IN
AV
DD
DV
CC
LOAD SWITCH
SECTION
CONTROL
SECTION
R3
R2
Q1
Q2
R1
06468-143
+
Figure 43. Load Switch Control Circuit
Figure 44 shows an example of the analog supplies powering up
before the digital supply. The circuit delays the AV
DD
power up
until after DV
CC
, as shown by the AV
DD
(delayed) line.
0
6468-144
AV
DD
AV
SS
DV
CC
AV
DD
(DELAYED)
t (sec)
Figure 44. Delayed Power Supplies Sequence Example
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the
AD5724/AD5734/AD5754 are mounted must be designed so the
analog and digital sections are separated and confined to certain
areas of the board. If the AD5724/AD5734/AD5754 are in a system
where multiple devices require an AGND to DGND connection,
the connection must be made at one point only. The star ground
point must be established as close as possible to the device.
The AD5724/AD5734/AD5754 must have ample supply bypassing
of a 10 μF capacitor in parallel with a 0.1 μF capacitor on each
supply located as close to the package as possible, ideally right up
against the device. The 10 μF capacitor is the tantalum bead type.
The 0.1 μF capacitor must have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
The power supply lines of the AD5724/AD5734/AD5754 must
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals, such as a data clock, must be shielded with
digital ground to avoid radiating noise to other devices of the
board, and must never run near the reference inputs. A ground
line routed between the SDIN and SCLK lines helps reduce
crosstalk between them (this is not required on a multilayer
board that has a separate ground plane, but separating the lines
does help). It is essential to minimize noise on the REFIN line
because any unwanted signals couple through to the DAC
outputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board must run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
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