Datasheet

AD5722/AD5732/AD5752
Rev. D | Page 5 of 32
AC PERFORMANCE CHARACTERISTICS
AV
DD
= 4.5 V
1
to 16.5 V; AV
SS
= −4.5 V to −16.5 V, or AV
SS
= 0 V; GND = 0 V; REFIN = 2.5 V; DV
CC
= 2.7 V to 5.5 V; R
LOAD
= 2 kΩ;
C
LOAD
= 200 pF; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
2
Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 10 12 μs 20 V step to ±0.03% FSR
7.5 8.5 μs 10 V step to ±0.03% FSR
5 μs 512 LSB step settling (16-bit resolution)
Slew Rate 3.5 V/μs
Digital-to-Analog Glitch Energy 13 nV-sec
Glitch Impulse Peak Amplitude 35 mV
Digital Crosstalk 10 nV-sec
DAC-to-DAC Crosstalk 10 nV-sec
Digital Feedthrough 0.6 nV-sec
Output Noise
0.1 Hz to 10 Hz Bandwidth 15 μV p-p 0x8000 DAC code
100 kHz Bandwidth 80 μV rms
Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code
1
For specified performance, the maximum headroom requirement is 0.9 V.
2
Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AV
DD
= 4.5 V to 16.5 V; AV
SS
= −4.5 V to −16.5 V, or AV
SS
= 0 V; GND = 0 V; REFIN = 2.5 V; DV
CC
= 2.7 V to 5.5 V; R
LOAD
= 2 kΩ; C
LOAD
=
200 pF; all specifications t
MIN
to t
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2 , 3
Limit at t
MIN
, t
MAX
Unit Description
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK high time
t
3
13 ns min SCLK low time
t
4
13 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
13 ns min
SCLK falling edge to SYNC
rising edge
t
6
100 ns min
Minimum SYNC
high time (write mode)
t
7
7 ns min Data setup time
t
8
2 ns min Data hold time
t
9
20 ns min
LDAC
falling edge to SYNC falling edge
t
10
130 ns min
SYNC
rising edge to LDAC falling edge
t
11
20 ns min
LDAC
pulse width low
t
12
10 μs max DAC output settling time
t
13
20 ns min
CLR
pulse width low
t
14
2.5 μs max
CLR
pulse activation time
t
15
4
13 ns min
SYNC
rising edge to SCLK falling edge
t
16
4
40 ns max SCLK rising edge to SDO valid (C
L SDO
5
= 15 pF)
t
17
200 ns min
Minimum SYNC
high time (readback/daisy-chain mode)
1
Guaranteed by characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, and Figure 4.
4
Daisy-chain and readback mode.
5
C
L SDO
= capacitive load on SDO output.