Datasheet

AD5722/AD5732/AD5752
Rev. D | Page 4 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS
3
DV
CC
= 2.7 V to 5.5 V, JEDEC compliant
Input High Voltage, V
IH
2 V
Input Low Voltage, V
IL
0.8 V
Input Current ±1 μA Per pin
Pin Capacitance 5 pF Per pin
DIGITAL OUTPUTS (SDO)
3
Output Low Voltage, V
OL
0.4 V DV
CC
= 5 V ± 10%, sinking 200 μA
Output High Voltage, V
OH
DV
CC
− 1 V DV
CC
= 5 V ± 10%, sourcing 200 μA
Output Low Voltage, V
OL
0.4 V DV
CC
= 2.7 V to 3.6 V, sinking 200 μA
Output High Voltage, V
OH
DV
CC
− 0.5 V DV
CC
= 2.7 V to 3.6 V, sourcing 200 μA
High Impedance Leakage
Current
−1 +1 μA
High Impedance Output
Capacitance
5 pF
POWER REQUIREMENTS
AV
DD
4.5 16.5 V
AV
SS
−4.5 −16.5 V
DV
CC
2.7 5.5 V
Power Supply Sensitivity
3
∆V
OUT
/∆ΑV
DD
−65 dB
AI
DD
3.25 mA/channel Outputs unloaded
2.4 mA/channel AV
SS
= 0 V, outputs unloaded
AI
SS
2.5 mA/channel Outputs unloaded
DI
CC
0.5 3 μA V
IH
= DV
CC
, V
IL
= GND
Power Dissipation 190 mW ±16.5 V operation, outputs unloaded
79 mW 16.5 V operation, AV
SS
= 0 V, outputs unloaded
Power-Down Currents
AI
DD
40 μA
AI
SS
40 μA
D
ICC
300 nA
1
For specified performance, the maximum headroom requirement is 0.9 V.
2
INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5752, the AD5732, and the AD5722, respectively.
3
Guaranteed by characterization; not production tested.