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Low Power HART Modem

Data Sheet

AD5700/AD5700-1

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FEATURES

HART-compliant fully integrated FSK modem

1200 Hz and 2200 Hz sinusoidal shift frequencies

115 μA maximum supply current in receive mode

Suitable for intrinsically safe applications

Integrated receive band-pass filter

Minimal external components required

Clocking optimized for various system configurations

Ultralow power crystal oscillator (60 μA maximum)

External CMOS clock source

Precision internal oscillator (AD5700-1only)

Buffered HART output—extra drive capability

8 kV HBM ESD rating

1.71 V to 5.5 V power supply

1.71 V to 5.5 V interface

−40°C to +125°C operation

4 mm × 4 mm LFCSP package

HART physical layer compliant

UART interface

APPLICATIONS

Field transmitters

HART multiplexers

PLC and DCS analog I/O modules

HART network connectivity

GENERAL DESCRIPTION

The AD5700/AD5700-1 are single-chip solutions, designed

and specified to operate as a HART® FSK half-duplex modem,

complying with the HART physical layer requirements. The

AD5700/AD5700-1 integrate all of the necessary filtering, signal

detection, modulating, demodulating and signal generation

functions, thus requiring few external components. The 0.5%

precision internal oscillator on the AD5700-1 greatly reduces

the board space requirements, making it ideal for line-powered

applications in both master and slave configurations. The maxi-

mum supply current consumption is 115 μA, making the AD5700/

AD5700-1 an optimal choice for low power loop-powered applica-

tions. Transmit waveforms are phase continuous 1200 Hz and

2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate

carrier detect circuitry and use a standard UART interface.

Table 1. Related Products

Part No. Description

AD5755-1 Quad-channel, 16-bit, serial input, 4 mA to 20 mA and

voltage output DAC, dynamic power control, HART

connectivity

AD5421 16-bit, serial input, loop powered, 4 mA to 20 mA DAC

AD5410/

AD5420

Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA

current source DACs

AD5412/

AD5422

Single-channel, 12-bit/16-bit, serial input, current

source and voltage output DACs

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

OSC

XTAL1

REF REF_EN AGNDDGND FILTER_SEL

CLKOUT

REG_CAP

RESET

DUPLEX

IOV

HART_OUT

ADC_IP

HART_IN

RXD

TXD

RTS

CLK_CFG0

CLK_CFG1

XTAL_EN

AD5700/AD5700-1

XTAL2

CONTROL LOGIC

10435-001

FSK

MODULATOR

VOLTAGE

REFERENCE

DAC

FSK

DEMODULATOR

BAND-PASS

FILTER AND

BIASING

ADC

BUFFER

Summary of content (24 pages)

PAGE 1
Low Power HART Modem AD5700/AD5700-1 Data Sheet FEATURES GENERAL DESCRIPTION HART-compliant fully integrated FSK modem 1200 Hz and 2200 Hz sinusoidal shift frequencies 115 μA maximum supply current in receive mode Suitable for intrinsically safe applications Integrated receive band-pass filter Minimal external components required Clocking optimized for various system configurations Ultralow power crystal oscillator (60 μA maximum) External CMOS clock source Precision internal oscillator (AD5700-1only) Bu
PAGE 2
AD5700/AD5700-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 FSK Modulator ........................................................................... 13 Applications ....................................................................................... 1 Connecting to HART_OUT ..................................................... 14 General Description ...........................................................
PAGE 3
Data Sheet AD5700/AD5700-1 SPECIFICATIONS VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, AGND = DGND, CLKOUT disabled, HART_OUT with 5 nF load, internal and external receive filter, internal reference; all specifications are from −40°C to +125°C and relate to both A and B models, unless otherwise noted. Table 2. Parameter 1 POWER REQUIREMENTS 2 VCC IOVCC VCC and IOVCC Current Consumption Demodulator Min Typ Max Unit 5.5 5.
PAGE 4
AD5700/AD5700-1 Parameter 1 DIGITAL OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage CD Assert 6 HART_IN INPUT5 Input Voltage Range HART_OUT OUTPUT Output Voltage Mark Frequency 7 Space Frequency7 Frequency Error Data Sheet Min 85 Unit 100 0.4 110 V V mV p-p REF 1.5 V V External reference source Internal reference enabled 505 mV p-p AC-coupled (2.2 µF), measured at HART_OUT pin with 160 Ω load (worst-case load), see Figure 17 and Figure 18 for HART_OUT voltage vs.
PAGE 5
Data Sheet AD5700/AD5700-1 TIMING CHARACTERISTICS VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1 t1 Limit at TMIN, TMAX 1 Unit Bit time 2 max t2 1 Bit time2 max t3 1 Bit time2 max t4 t5 t6 6 6 10 Bit times2 max Bit times2 max Bit times2 max t7 2.1 ms typ t8 t9 6 25 ms typ µs typ t10 t11 10 30 ms typ µs typ 1 2 Description Carrier start time. Time from RTS falling edge to carrier reaching its first peak. See Figure 3.
PAGE 6
AD5700/AD5700-1 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
PAGE 7
Data Sheet AD5700/AD5700-1 20 XTAL2 19 AGND 21 XTAL1 22 DGND 24 FILTER_SEL 23 REF_EN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 18 VCC XTAL_EN 1 CLKOUT 2 CLK_CFG0 3 AD5700/ AD5700-1 CLK_CFG1 4 TOP VIEW (Not to Scale) RESET 5 17 ADC_IP 16 HART_IN 15 REF 14 HART_OUT CD 6 NOTES 1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND OR DGND, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED.
PAGE 8
AD5700/AD5700-1 Pin No. 19 20 Mnemonic AGND XTAL2 21 XTAL1 22 DGND 23 REF_EN 24 FILTER_SEL EPAD EPAD Data Sheet Description Analog Circuitry Ground Reference Connection. Connection for External 3.6864 MHz Crystal. Do not connect to this pin if using the internal RC oscillator (AD5700-1 only) or an external clock source. Connection for External 3.6864 MHz Crystal or External Clock Source Input. Tie this pin to ground if using the internal RC oscillator (AD5700-1 only).
PAGE 9
Data Sheet AD5700/AD5700-1 TYPICAL PERFORMANCE CHARACTERISTICS 1.4 1.2 1.4 TA = 25°C; VCC = IOVCC = 3.3V; INT VREF RTS AND TXD DC LEVELS HAVE BEEN ADJUSTED FOR CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE FROM 0V TO 3.3V. 1.2 1.0 1.0 CD 0.8 HART SIGNAL (V) RTS HART_OUT (V) TA = 25°C; VCC = IOVCC = 3.3V; INT VREF CD AND RXD DC LEVELS HAVE BEEN ADJUSTED FOR CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE FROM 0V TO 3.3V. t1 0.6 TXD 0.4 0.2 t5 0.8 0.6 RXD 0.4 0.
PAGE 10
AD5700/AD5700-1 200 0 TA = 25°C VCC = IOVCC = 1.71V TO 5.5V DEV 1 INT REF REG_CAP IS CONNECTED TO VCC FOR SUPPLIES OF ≤ 2.0V 180 160 –2 TA = 25°C VCC = IOVCC = 3.3V INT VREF –4 140 –6 GAIN (dB) MOD ICC AND IOICC 100 80 DEMOD ICC AND IOICC –8 –10 –12 60 –14 40 –16 20 –18 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VCC = IOVCC (V) 4.5 5.0 5.5 6.0 –20 100 2.5 TA = 25°C; VCC = IOVCC = 3.3V; INT VREF CLK CONFIG = XTAL OSCILLATOR IOICC = 41µA 600 1k FREQUENCY (Hz) 10k Figure 12.
PAGE 11
Data Sheet AD5700/AD5700-1 500 1.5012 TA = 25°C 1.5010 VCC = IOVCC = 1.71V TO 5.5V TA = 25°C VCC = IOVCC = 3.3V 495 INT V REF HART_OUT (mV p-p) 1.5006 1.5004 1.5002 1.5000 490 485 1200Hz 2200Hz 480 475 2.2µF 1.4998 HART_OUT 1.5 2.0 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 6.0 465 10435-012 1.4994 1.0 0 Figure 15. Reference Voltage vs. VCC 1.5006 1.5004 200 400 600 800 RLOAD (Ω) || WITH 22nF TO GND 1000 1200 Figure 17. HART_OUT Voltage vs. RLOAD 505 VCC = IOVCC = 2.
PAGE 12
AD5700/AD5700-1 Data Sheet TERMINOLOGY VCC and IOVCC Current Consumption This specification gives a summation of the current consumption of both the VCC and the IOVCC supplies. Figure 11 shows separate measurements for VCC and IOVCC currents vs. varying capacitive loads, in transmit mode. Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/µA.
PAGE 13
Data Sheet AD5700/AD5700-1 THEORY OF OPERATION A single-chip solution, the AD5700/AD5700-1 not only integrate the modulation and demodulation functions, but also contain an internal reference, an integrated receive band-pass filter (which has the flexibility of being bypassed if required), and an internally buffered HART output, giving a high output drive capability and removing the need for external buffering. The AD5700-1 option also contains a precision internal RC oscillator.
PAGE 14
AD5700/AD5700-1 Data Sheet CONNECTING TO HART_OUT FSK DEMODULATOR The HART_OUT pin is dc biased to 0.75 V and should be capacitively coupled to the load. The current consumption specifications in Table 2 are based on driving a 5 nF load. If the application requires a larger load value, more current is required.
PAGE 15
Data Sheet AD5700/AD5700-1 The internal filter configuration is shown in Figure 24. This option is beneficial where cost or board space is a large concern because it removes the need for multiple external components. This configuration achieves an 8 kV ESD HBM rating but requires extra external protection circuitry for EMC and surge protection purposes if used in harsh industrial environments. CMOS Clock Input A CMOS clock input can also be used to generate a clock for the AD5700/AD5700-1.
PAGE 16
AD5700/AD5700-1 Data Sheet Table 7. Clock Configuration Options XTAL_EN CLK_CFG1 CLK_CFG0 CLKOUT Description 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 No output No output No output 1.2288 MHz output No output 3.6864 MHz output 1.8432 MHz output 1.2288 MHz output 3.6864 MHz CMOS clock connected at XTAL1 pin 1.
PAGE 17
Data Sheet AD5700/AD5700-1 APPLICATIONS INFORMATION shows an example of a HART-enabled current input module that contains transient voltage protection circuitry, which is very important in harsh industrial control environments. SUPPLY DECOUPLING It is recommended to decouple the VCC and IOVCC supplies with 10 μF in parallel with 0.1 μF capacitors to ground. For many applications, 1 μF in parallel with 0.1 μF ceramic capacitors to ground should be sufficient. The REG_CAP voltage of 1.
PAGE 18
AD5700/AD5700-1 Data Sheet combination of Analog Devices industrial converters and the AD5700/AD5700-1 greatly simplifies system design, enhancing reliability while reducing overall PCB size. As previously mentioned, Figure 29 shows an example secondary HART device, incorporating two-stage protection circuitry.
PAGE 19
Data Sheet AD5700/AD5700-1 OPTIONAL EMC FILTER OPTIONAL MOSFET DN2540 BSP129 10µF 4.7µF T1 0.1µF 200kΩ IODVDD DVDD REGOUT REGIN VLOOP RANGE0 RANGE1 DRIVE ALARM_CURRENT_DIRECTION RINT/REXT VLOOP SYNC SCLK SDIN SDO FAULT LDAC VZ = 4.7V 0.1µF REXT2 REG_SEL2 REFOUT1 REFIN 0.1µF REG_SEL1 R1 REFOUT2 1µF LOOP– REXT1 COM OPTIONAL RESISTOR CIN COM SETS REGULATOR VOLTAGE 47nF 168nF VCC AD5700/AD5700-1 TXD RXD RTS CD HART_OUT REF 1µF 1.2MΩ 300pF ADC_IP AGND DGND 1.
PAGE 20
AD5700/AD5700-1 Data Sheet 3.3V ADuCM360 AD5421 VDD PRESSURE SENSOR SIMULATION ADC 0 3.3V REGIN + V-REGULATOR MICROCONTROLLER VLOOP SRAM FLASH CLOCK RESET WATCHDOG LEXC TEMPERATURE SENSOR PT100 ADC TEMPERATURE SENSOR SPI COM ADC 1 4.7nF DAC COM 50Ω WATCHDOG TIMER TEST CONNECTOR UART T1: CD T2: RTS T3: COM CIN LOOP– – T4: TEST VCC AD5700 HART_OUT 3.3V C_HART C_SLEW REF HART MODEM ADC_IP HART INPUT FILTER 10435-029 AGND DGND Figure 32.
PAGE 21
Data Sheet AD5700/AD5700-1 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 2.20 2.10 SQ 2.00 6 7 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 06-11-2012-A COPLANARITY 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. Figure 33.
PAGE 22
AD5700/AD5700-1 Data Sheet NOTES Rev.
PAGE 23
Data Sheet AD5700/AD5700-1 NOTES Rev.