Datasheet

AD569
REV. A
–3–
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance Only and are not subject to test.
+V
S
= +12 V; –V
S
= –12 V; +V
REF
= +5 V; –V
REF
= –5 V excepts where stated.
Parameter Limit Units Test Conditions/Comments
Output Voltage Settling 5 µs max No Load Applied
(Time to ±0.001% FS 3 µs typ (DAC output measured from falling edge of
LDAC.)
For FS Step) 6 µs max V
OUT
Load = 1 kΩ, C
LOAD
= 1000 pF.
4 µs typ (DAC output measured from falling edge of LDAC. )
Digital-to-Analog Glitch 500 nV-sec typ Measured with V
REF
= 0 V. DAC registers alternatively loaded
Impulse with input codes of 8000
H
and 0FFF
H
(worst-case
transition). Load = 1 kΩ.
Multiplying Feedthrough –100 dB max +V
REF
= 1 V rms 10 kHz sine wave,
–V
REF
= 0 V
Output Noise Voltage 40 nV/ÏHz typ Measured between V
OUT
and –V
REF
Density (1 kHz-1 MHz)
TIMING CHARACTERISTICS
(+V
S
= +12 V, –V
S
= –12 V, V
IH
= 2.4 V, V
IL
= 0.4 V,T
MIN
to T
MAX
)
Parameter Limit Units Test Conditions/Comments
Case A 150 ns Pulse on HBE, LBE, and LDAC
T
HS
= 140 ns min, T
HH
= 10 ns min
t
WC
120 ns min CS Pulse Width
t
SC
60 ns min CS Data Setup Time
t
HC
20 ns min CS Data Hold Time
Case B None
t
WB
70 ns min HBE, LBE Pulse Width
t
SB
80 ns min HBE, LBE Data Setup Time
t
HB
20 ns min HBE, LBE Data Hold Time
t
SCS
120 ns min CS Setup Time
t
HCS
10 ns min CS Hold Time
t
WD
120 ns min LDAC Pulse Width
Case C None
t
WB
120 ns min HBE, LBE Pulse Width
t
SB
80 ns min HBE, LBE Data Setup Time
t
HB
20 ns min HBE, LBE Data Hold Time
t
SCS
120 ns min CS Setup Time
t
HCS
10 ns min CS Hold Time
Figure 2a. AD569 Timing Diagram – Case B
Figure 2b. AD569 Timing Diagram – Case C
Figure 1. AD569 Timing Diagram – Case A