Datasheet

AD5697R Data Sheet
Rev. 0 | Page 6 of 28
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V; 1.8 V ≤ V
LOGIC
≤ 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. See Figure 2.
Table 4.
Parameter
1
Min Max
Unit Test Conditions/Comments
t
1
2.5 µs SCL cycle time
t
2
0.6 µs SCL high time, t
HIGH
t
3
1.3 µs SCL low time, t
LOW
t
4
0.6 µs Start/repeated start condition hold time, t
HD,STA
t
5
100 ns Data setup time, t
SU,DAT
t
6
2
0 0.9 µs Data hold time, t
HD,DAT
t
7
0.6 µs Setup time for repeated start, t
SU,STA
t
8
0.6 µs Stop condition setup time, t
SU,STO
t
9
1.3 µs Bus free time between a stop and a start condition, t
BUF
t
10
0 300 ns Rise time of SCL and SDA when receiving, t
R
t
11
20 + 0.1C
B
3
300 ns Fall time of SDA and SCL when transmitting/receiving, t
F
t
12
20 ns
LDAC
pulse width
t
13
400 ns SCL rising edge to
LDAC
rising edge
C
B
3
400 pF Capacitive load for each bus line
1
Guaranteed by design and characterization; not production tested.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
minimum of the SCL signal) to bridge the undefined region of the
falling edge of the SCL.
3
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Figure 2. 2-Wire Serial Interface Timing Diagram
SCL
SDA
t
1
t
3
LDAC
1
LDAC
2
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
t
4
t
6
t
5
t
7
t
8
t
2
t
13
t
4
t
11
t
10
t
12
t
12
t
9
11253-002