Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

Dual, 12-Bit nanoDAC+

with 2 ppm/°C Reference, I

C Interface

Data Sheet

AD5697R

Rev. 0 Document Feedback

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FEATURES

Low drift 2.5 V reference: 2 ppm/°C typical

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of full-scale range (FSR)

maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

Low glitch: 0.5 nV-sec

400 kHz I

C-compatible serial interface

Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating

Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Base station power amplifiers

Process controls (programmable logic controller [PLC] I/O cards)

Industrial automation

Data acquisition systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD5697R, a member of the nanoDAC+™ family, is a low power,

dual, 12-bit buffered voltage output digital-to-analog converter

(DAC). The device includes a 2.5 V, 2 ppm/°C internal reference

(enabled by default) and a gain select pin giving a full-scale output

of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates from

a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design,

and exhibits less than 0.1% FSR gain error and 1.5 mV offset

error performance. The device is available in a 3 mm × 3 mm

LFCSP and a TSSOP package.

The AD5697R also incorporates a power-on reset circuit and a

RSTSEL pin that ensure that the DAC outputs power up to zero

scale or midscale and remain there until a valid write takes

place. It contains a per channel power-down feature that reduces

the current consumption of the device to 4 µA at 3 V while in

power-down mode.

The AD5697R uses a versatile 2-wire serial interface that operates

at clock rates up to 400 kHz and includes a V

LOGIC

pin intended

for 1.8 V/3 V/5 V logic.

Table 1. Dual nanoDAC+ Devices

Interface Reference 16-Bit 12-Bit

SPI Internal AD5689R AD5687R

External

AD5689

AD5687

C Internal AD5697R

External

PRODUCT HIGHLIGHTS

1. Precision DC Performance.

TUE: ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

2. Low Drift 2.5 V On-Chip Reference.

2 ppm/°C typical temperature coefficient

5 ppm/°C maximum temperature coefficient

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP

16-lead TSSOP

SCL

LOGIC

SDA

INPUT

DAC

STRING

DAC A

BUFFER

OUT

INPUT

DAC

STRING

DAC B

BUFFER

OUT

REFGND

POWER-

DOWN

LOGIC

POWER-ON

RESET

GAIN =

×1/×2

INTERFACE LOGIC

RSTSEL GAINLDAC RESET

AD5697R

2.5V

REFERENCE

11253-001

Summary of content (28 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of full-scale range (FSR) maximum VREF GND AD5697R 2.5V REFERENCE VLOGIC INTERFACE LOGIC SCL SDA Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.
PAGE 2
AD5697R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Operation ......................................................................... 19 Applications ....................................................................................... 1 Write Operation.......................................................................... 19 Functional Block Diagram ................................................
PAGE 3
Data Sheet AD5697R SPECIFICATIONS VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; and all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; and CL = 200 pF. Table 2.
PAGE 4
AD5697R Parameter LOGIC OUTPUTS (SDA)2 Output Low Voltage, VOL Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD IDD Normal Mode 9 All Power-Down Modes 10 Data Sheet Min Typ Max Unit Test Conditions/Comments 0.4 V pF ISINK = 3 mA 5.5 3 5.5 5.5 V µA V V 0.7 1.3 4 6 mA mA µA µA 4 1.8 2.7 VREF + 1.5 0.59 1.1 1 Gain = 1 Gain = 2 VIH = VDD, VIL = GND, VDD = 2.7 V to 5.
PAGE 5
Data Sheet AD5697R AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization; not production tested. Table 3.
PAGE 6
AD5697R Data Sheet TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2. Table 4. Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 20 + 0.1CB 3 20 400 Parameter 1 t1 t2 t3 t4 t5 t6 2 t7 t8 t9 t10 t11 t12 t13 C B3 Max Unit µs µs µs µs ns µs µs µs µs ns ns ns ns pF 0.
PAGE 7
Data Sheet AD5697R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND 1 SDA and SCL to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free (J-STD-020) ESD 2 FICDM 1 2 Rating −0.3 V to +7 V −0.
PAGE 8
AD5697R Data Sheet VOUTA 1 GND 2 VDD 3 AD5697R 10 A0 GAIN 8 LDAC 7 SDA 6 VOUTB 5 11253-003 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. RSTSEL 15 RESET VOUTA 3 14 A1 SCL NC 9 VLOGIC NC 4 16 2 VREF 1 12 A1 11 SCL GND 4 AD5697R 13 VDD 5 TOP VIEW (Not to Scale) 12 A0 NC 6 11 VLOGIC VOUTB 7 10 GAIN SDA 8 9 LDAC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3.
PAGE 9
Data Sheet AD5697R TYPICAL PERFORMANCE CHARACTERISTICS 1600 DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 2.5015 2.5010 VDD = 5V 1400 1200 1000 NSD (nV/ Hz) VREF (V) 2.5005 2.5000 2.4995 800 600 2.4990 400 2.4985 200 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 10 11253-005 2.4980 –40 VDD = 5V TA = 25°C 1k 10k 100k 1M FREQUENCY (MHz) Figure 5. Internal Reference Voltage vs. Temperature 90 100 11253-009 2.5020 Figure 8. Internal Reference Noise Spectral Density vs.
PAGE 10
AD5697R Data Sheet 2.5002 TA = 25°C 10 D1 8 2.5000 6 4 D3 ERROR (LSB) VREF (V) 2.4998 2.4996 2.4994 2 INL 0 DNL –2 –4 2.4992 –6 –8 4.0 4.5 5.0 5.5 VDD (V) –10 –40 10 60 110 TEMPERATURE (°C) Figure 14. INL Error and DNL Error vs. Temperature 10 8 8 6 6 4 4 ERROR (LSB) 10 2 0 –2 2 DNL –2 –4 –6 –6 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –8 –10 0 625 1250 1875 INL 0 –4 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.
PAGE 11
Data Sheet AD5697R 1.5 0.10 0.08 1.0 0.04 0.5 FULL-SCALE ERROR 0.02 0 ERROR (mV) GAIN ERROR –0.02 0 OFFSET ERROR –0.5 –0.04 –0.06 –1.0 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –0.10 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –1.5 2.7 11253-018 –0.08 ZERO-CODE ERROR 3.2 3.7 4.2 4.7 11253-021 ERROR (% of FSR) 0.06 5.2 SUPPLY VOLTAGE (V) Figure 17. Gain Error and Full-Scale Error vs. Temperature Figure 20.
PAGE 12
Data Sheet 0 1.0 –0.01 0.8 –0.02 0.6 –0.03 0.4 –0.04 0.2 ΔVOUT (V) SINKING 2.7V –0.05 –0.06 –0.2 –0.4 –0.08 –0.6 SOURCING 5V SOURCING 2.7V –0.8 40000 50000 60000 65535 –1.0 CODE 0 10 20 25 30 Figure 26. Headroom/Footroom vs. Load Current 7 VDD = 5V TA = 25°C EXTERNAL REFERENCE = 2.5V VDD = 5V 6 TA = 25°C GAIN = 2 INTERNAL 5 REFERENCE = 2.5V 20 4 15 VOUT (V) HITS 15 LOAD CURRENT (mA) Figure 23. Total Unadjusted Error vs. Code 25 5 11253-027 VDD = 5V –0.
PAGE 13
Data Sheet AD5697R 3 CHANNEL A CHANNEL B SYNC 1.4 GAIN = 2 FULL SCALE 1.0 2 ZERO CODE VOUT (V) CURRENT (mA) 1.2 0.8 EXTERNAL REFERENCE, FULL SCALE 0.6 GAIN = 1 1 0.4 0.2 60 110 0 –5 TEMPERATURE (°C) 0 10 Figure 32. Exiting Power-Down to Midscale Figure 29. Supply Current vs. Temperature 4.0 3.5 5 TIME (µs) 11253-033 10 11253-030 0 –40 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V 2.5008 DAC A DAC B 3.0 2.5003 VOUT (V) VOUT (V) 2.5 2.0 2.4998 1.5 2.
PAGE 14
AD5697R Data Sheet 20 T VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V 0 –20 THD (dBV) –40 1 –60 –80 –100 –120 –140 VDD = 5V TA = 25°C EXTERNAL REFERENCE = 2.5V A CH1 802mV 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 FREQUENCY (Hz) Figure 35. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 11253-039 M1.0s –180 11253-036 CH1 10µV –160 Figure 38. Total Harmonic Distortion at 1 kHz 4.0 T 0nF 0.1nF 10nF 0.22nF 4.7nF 3.9 3.8 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.
PAGE 15
Data Sheet AD5697R TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 12. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 16
AD5697R Data Sheet DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec.
PAGE 17
Data Sheet AD5697R THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5697R is a dual, 12-bit, serial input, voltage output DAC with an internal reference. The part operates from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5697R in a 24-bit word format via a 2-wire serial interface. The AD5697R incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state.
PAGE 18
AD5697R Data Sheet SERIAL INTERFACE Table 8. Address Commands The AD5697R has a 2-wire I2C-compatible serial interface (refer to I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). See Figure 2 for a timing diagram of a typical write sequence. The AD5697R can be connected to an I2C bus as a slave device, under the control of a master device. The AD5697R can support standard (100 kHz) and fast (400 kHz) data transfer modes.
PAGE 19
Data Sheet AD5697R SERIAL OPERATION 2. The AD5697R has a 7-bit slave address. The five MSBs are 00011 and the two LSBs (A1 and A0) are set by the state of the A0 and A1 address pins. The ability to make hardwired changes to A0 and A1 allows the user to incorporate up to four of these devices on one bus, as outlined in Table 9. 3. Table 9.
PAGE 20
AD5697R Data Sheet READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5697R DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the control byte that determines both the read command that is to follow and the pointer address to read from, which is also acknowledged by the DAC.
PAGE 21
Data Sheet AD5697R POWER-DOWN OPERATION The AD5697R contains three separate power-down modes. Command 0100 is designated for the power-down function (see Table 7). These power-down modes are software programmable by setting eight bits, Bit DB7 to Bit DB0, in the shift register. There are two bits associated with each DAC channel. Table 10 shows how the state of the two bits corresponds to the mode of operation of the device. amplifier to a resistor network of known values.
PAGE 22
AD5697R Data Sheet LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5697R DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC register are controlled by the LDAC pin. Command 0101 is reserved for this software LDAC mask function, which allows the address bits to be ignored. Writing to the DAC using Command 0101 loads the 4-bit LDAC register (DB3 to DB0).
PAGE 23
Data Sheet AD5697R HARDWARE RESET (RESET) SOLDER HEAT REFLOW RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the power-on reset select (RSTSEL) pin. It is necessary to keep RESET low for a minimum amount of time to complete the operation . When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed.
PAGE 24
AD5697R Data Sheet THERMAL HYSTERESIS 9 Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. 8 7 6 5 4 3 2 1 0 –200 –150 –100 –50 DISTORTION (ppm) Figure 50. Thermal Hysteresis Rev. 0 | Page 24 of 28 0 50 11253-051 HITS Thermal hysteresis data is shown in Figure 50. It is measured by sweeping temperature from ambient to −40°C, then to +105°C, and returning to ambient.
PAGE 25
Data Sheet AD5697R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5697R is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal. AD5697R-TO-ADSP-BF531 INTERFACE The I2C interface of the AD5697R is designed to be easily connected to industry-standard DSPs and microcontrollers.
PAGE 26
AD5697R Data Sheet OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 0.80 0.75 0.70 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E TOP VIEW 4 5 8 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 54.
PAGE 27
Data Sheet AD5697R NOTES Rev.