Datasheet

AD5696R/AD5695R/AD5694R Data Sheet
Rev. B | Page 24 of 32
LOAD DAC (HARDWARE
LDAC
PIN)
The AD5696R/AD5695R/AD5694R DACs have double
buffered interfaces consisting of two banks of registers:
input registers and DAC registers. The user can write to
any combination of the input registers. Updates to the DAC
register are controlled by the
LDAC
pin.
Figure 54. Simplified Diagram of Input Loading Circuitry for a Single DAC
Instantaneous DAC Updating (
LDAC
Held Low)
LDAC
is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the 24
th
clock and the output
begins to change (see Table 13).
Deferred DAC Updating (
LDAC
is Pulsed Low)
LDAC
is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
updated by taking
LDAC
low after the 24
th
clock. The update
now occurs on the falling edge of
LDAC
.
LDAC
MASK REGISTER
Command 0101 is reserved for this software
LDAC
function.
Address bits are ignored. Writing to the DAC, using Command
0101, loads the 4-bit
LDAC
register (DB3 to DB0). The default
for each channel is 0; that is, the
LDAC
pin works normally.
Setting the bits to 1 forces this DAC channel to ignore transitions
on the
LDAC
pin, regardless of the state of the hardware
LDAC
pin. This flexibility is useful in applications where the user
wishes to select which channels respond to the
LDAC
pin.
Table 12.
LDAC
Overwrite Definition
Load
LDAC
Register
LDAC
Bits
(DB3 to DB0)
LDAC
Pin
LDAC
Operation
0 1 or 0 Determined by the
LDAC
pin.
1 X
1
DAC channels update and
override the
LDAC
pin. DAC
channels see
LDAC
as 1.
1
X = don’t care.
The
LDAC
register gives the user extra flexibility and control
over the hardware
LDAC
pin (see Table 12). Setting the
LDAC
bits (DB0 to DB3) to 0 for a DAC channel means that this
channels update is controlled by the hardware
LDAC
pin.
Table 13. Write Commands and
LDAC
Pin Truth Table
1
Commands Description
Hardware
LDAC
Pin State
Input Register
Contents
DAC Register Contents
0001 Write to Input Register n (dependent on
LDAC
) V
LOGIC
Data update No change (no update)
GND
2
Data update Data update
0010
Update DAC Register n with contents of Input
Register n
V
LOGIC
No change
Updated with input register
contents
GND No change Updated with input register
contents
0011 Write to and update DAC Channel n V
LOGIC
Data update Data update
GND Data update Data update
1
A high to low hardware
LDAC
pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that
are not masked (blocked) by the
LDAC
mask register.
2
When LDAC is permanently tied low, the LDAC mask bits are ignored.
SDO
SCL
V
OUT
DAC
REGISTER
INPUT SHIFT
REGISTER
OUTPUT
AMPLIFIER
LDAC
REFIN
INPUT
REGISTER
12-/14-/16-BIT
DAC
10486-059