Datasheet

AD5696R/AD5695R/AD5694R Data Sheet
Rev. B | Page 22 of 32
READ OPERATION
When reading data back from the AD5696R DACs, the user
begins with an address byte (R/
W
= 0), after which the DAC
acknowledges that it is prepared to receive data by pulling SDA
low. This address byte must be followed by the control byte that
determines both the read command that is to follow and the
pointer address to read from, which is also acknowledged by
the DAC. The user configures which channel to read back and
sets the readback command to active using the control byte.
Following this, there is a repeated start condition by the master
and the address is resent with R/
W
= 1. This is acknowledged
by the DAC, indicating that it is prepared to transmit data.
Two bytes of data are then read from the DAC, as shown in
Figure 52. A NACK condition from the master, followed by a
STOP condition, completes the read sequence. Default readback
is Channel A if more than one DAC is selected.
MULTIPLE DAC READBACK SEQUENCE
The user begins with an address byte (R/
W
= 0), after which the
DAC acknowledges that it is prepared to receive data by pulling
SDA low. This address byte must be followed by the control
byte, which is also acknowledged by the DAC. The user
configures which channel to start the readback using the
control byte. Following this, there is a repeated start condition
by the master and the address is resent with R/
W
= 1. This is
acknowledged by the DAC, indicating that it is prepared to
transmit data. The first two bytes of data are then read from the
DAC Input Register n selected using the control byte, most
significant byte first as shown in
Figure 52. The next two bytes
read back are the contents of DAC Input Register n + 1, the next
bytes read back are the contents of DAC Input Register n + 2.
Data continues to be read from the DAC input registers in this
auto-incremental fashion, until a NACK followed by a stop
condition follows. If the contents of DAC Input Register D are
read out, the next two bytes of data that are read are from the
contents of DAC Input Register A.
Figure 52. I
2
C Read Operation
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
1
1000 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
9 91
START BY
MASTER
ACK. BY
MASTER
ACK. BY
MASTER
SCL
SCL
SDA
1 9 91
1 9 91
ACK. BY
MASTER
REPEATED START BY
MASTER
ACK. BY
MASTER
FRAME 4
MOST SIGNIFICANT
DATA BYTE n
FRAME 3
SLAVE ADDRESS
ACK. BY
MASTER
NACK. BY
MASTER
STOP BY
MASTER
FRAME 4
MOST SIGNIFICANT
DATA BYTE n – 1
FRAME 3
SLAVE ADDRESS
SIGNIFICANT DATA BYTE n
1000 1 A1 A0 R/W DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
SDA
SCL
(CONTINUED)
SDA
(CONTINUED)
DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
10486-304