Datasheet
Data Sheet AD5696R/AD5695R/AD5694R
Rev. B | Page 21 of 32
SERIAL OPERATION
The AD5696R/AD5695R/AD5694R each have a 7-bit slave
address. The five MSBs are 00011 and the two LSBs (A1, A0)
are set by the state of the A0 and A1 address pins. The ability
to make hardwired changes to A0 and A1 allows the user to
incorporate up to four of these devices on one bus, as outlined
in Table 9.
Table 9. Device Address Selection
A0 Pin Connection A1 Pin Connection A0 A1
GND GND 0 0
V
LOGIC
GND 1 0
GND V
LOGIC
0 1
V
LOGIC
V
LOGIC
1 1
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the 9
th
clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to, or read from, its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10
th
clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the 9
th
clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10
th
clock pulse, and then high during the 10
th
clock pulse to establish a stop condition.
WRITE OPERATION
When writing to the AD5696R/AD5695R/AD5694R, the user
must begin with a start command followed by an address byte
(R/
W
= 0), after which the DAC acknowledges that it is
prepared to receive data by pulling SDA low. The AD5696R/
AD5695R/AD5694R require two bytes of data for the DAC
and a command byte that controls various DAC functions.
Three bytes of data must, therefore, be written to the DAC with
the command byte followed by the most significant data byte
and the least significant data byte, as shown in Figure 51. All
these data bytes are acknowledged by the AD5696R/AD5695R/
AD5694R. A stop condition follows.
Figure 51. I
2
C Write Operation
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
19 91
SCL
START BY
MASTER
ACK. BY
AD56x6
ACK. BY
AD56x6
SDA
R/W
DB23A0A11000 1 DB22 DB21 DB20 DB19 DB18 DB17 DB16
19 91
ACK. BY
AD56x6
ACK. BY
AD56x6
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
FRAME 3
MOST SIGNIFICANT
DATA BYTE
STOP BY
MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10486-303