Datasheet

Data Sheet AD5696R/AD5695R/AD5694R
Rev. B | Page 19 of 32
SERIAL INTERFACE
The AD5696R/AD5695R/AD5694R have 2-wire I
2
C-compati-
ble serial interfaces (refer to I
2
C-Bus Specification, Version 2.1,
January 2000, available from Philips Semiconductor). See Figure 2
for a timing diagram of a typical write sequence. The AD5696R/
AD5695R/AD5694R can be connected to an I
2
C bus as a slave
device, under the control of a master device. The AD5696R/
AD5695R/AD5694R support standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for 10-
bit addressing and general call addressing. Power should not be
removed while the device is connected to an active I
2
C bus.
Input Shift Register
The input shift register of the AD5696R/AD5695R/AD5694R is
24 bits wide. Data is loaded into the device as a 24-bit word
under the control of a serial clock input, SCL. The first eight
MSBs make up the command byte. The first four bits are the
command bits (C3, C2, C1, C0) that control the mode of
operation of the device (see Table 7). The last 4 bits of first byte
are the address bits (DAC A, DAC B, DAC C, DAC D) (see
Table 8).
The data-word comprises 16-bit, 14-bit, or 12-bit input code,
followed by four, two, or zero don’t care bits for the AD5696R,
AD5695R, and AD5694R, respectively (see Figure 48, Figure 49,
and Figure 50). These data bits are transferred to the input
register on the 24 falling edges of SCL.
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DACs, depending on the
address bits selected.
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
0
0
0
0
No operation
0
0
0
1
Write to Input Register n (dependent on
LDAC
)
0 0 1 0
Update DAC Register n with contents of Input
Register n
0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1
Hardware
LDAC
mask register
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Internal reference setup register
1 0 0 0 Reserved
Reserved
1 1 1 1 Reserved
Table 8. Address Commands
Address (n)
Selected DAC Channel
1
DAC D DAC C DAC B DAC A
0 0 0 1 DAC A
0 0 1 0 DAC B
0 1 0 0 DAC C
1 0 0 0 DAC D
0 0 1 1 DAC A and DAC B
1
1 1 1 1 All DACs
1
Any combination of DAC channels can be selected using the address bits.
Figure 48. AD5696R Input Shift Register Content
Figure 49. AD5695R Input Shift Register Content
DB23 DB22 DB21 DB20 DB19 DB18
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2 DB1 DB0
C3 C2 C1 C0 DAC D DAC C DAC B DAC A D11
D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0 X X X X
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
10486-300
DB23 DB22
DB21 DB20 DB19 DB18 DB17
DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2 DB1 DB0
C3 C2
C1 C0 DAC D DAC C DAC B DAC A D13
D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
X X
COMMAND DAC ADDRESS DAC DATA
DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
10486-301