Datasheet

AD5696/AD5694 Data Sheet
Rev. A | Page 6 of 24
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; 1.8 V ≤ V
LOGIC
≤ 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
1, 2
Min Max Unit Description
t
1
2.5 μs SCL cycle time
t
2
0.6 μs t
HIGH
, SCL high time
t
3
1.3 μs t
LOW
, SCL low time
t
4
0.6 μs t
HD,STA
, start/repeated start hold time
t
5
100 ns t
SU,DAT
, data setup time
t
6
3
0 0.9 μs t
HD,DAT
, data hold time
t
7
0.6 μs t
SU,STA
, repeated start setup time
t
8
0.6 μs t
SU,STO
, stop condition setup time
t
9
1.3 μs t
BUF
, bus free time between a stop condition and a start condition
t
10
4
0 300 ns t
R
, rise time of SCL and SDA when receiving
t
11
4, 5
20 + 0.1C
B
300 ns t
F
, fall time of SCL and SDA when transmitting/receiving
t
12
20 ns
LDAC
pulse width
t
13
400 ns
SCL rising edge to LDAC
rising edge
t
SP
6
0 50 ns Pulse width of suppressed spike
C
B
5
400 pF Capacitive load for each bus line
1
See Figure 2.
2
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) to bridge the undefined region of the SCL
falling edge.
4
t
R
and t
F
are measured from 0.3 × V
DD
to 0.7 × V
DD
.
5
C
B
is the total capacitance of one bus line in pF.
6
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
Timing Diagram
Figure 2. 2-Wire Serial Interface Timing Diagram
SCL
SDA
t
1
t
3
LDAC
1
LDAC
2
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
t
4
t
6
t
5
t
7
t
8
t
2
t
13
t
4
t
11
t
10
t
12
t
12
t
9
10799-002