Datasheet

Data Sheet AD5696/AD5694
Rev. A | Page 3 of 24
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V; V
REF
= 2.5 V; 1.8 V ≤ V
LOGIC
≤ 5.5 V; R
L
= 2 kΩ; C
L
= 200 pF; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A Grade
B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
1
STATIC PERFORMANCE
2
AD5696
Resolution 16 16 Bits
Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2
±2 ±8 ±1 ±3 LSB Gain = 1
Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by
design
AD5694
Resolution 12 12 Bits
Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB
Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by
design
Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register
Offset Error +0.1 ±4 +0.1 ±1.5 mV
Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of FSR All 1s loaded to DAC register
Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR
Total Unadjusted Error
±0.01
±0.25
±0.01
±0.1
% of FSR
Gain = 2
±0.25 ±0.2 % of FSR Gain = 1
Offset Error Drift
3
±1 ±1 µV/°C
Gain Temperature
Coefficient
3
±1 ±1 ppm Of FSR/°C
DC Power Supply Rejection
Ratio
3
0.15 0.15 mV/V DAC code = midscale; V
DD
=
5 V ± 10%
DC Crosstalk
3
±2 ±2 µV Due to single channel, full-
scale output change
±3
±3
µV/mA
Due to load current change
±2 ±2 µV Due to power-down (per
channel)
OUTPUT CHARACTERISTICS
3
Output Voltage Range 0 V
REF
0 V
REF
V Gain = 1
0 2 × V
REF
0 2 × V
REF
V Gain = 2 (see Figure 20)
Capacitive Load Stability 2 2 nF R
L
= ∞
10 10 nF R
L
= 1 kΩ
Resistive Load
4
1 1 kΩ
Load Regulation DAC code = midscale
80 80 µV/mA 5 V ± 10%; −30 mA ≤ I
OUT
≤
+30 mA
80 80 µV/mA 3 V ± 10%; −20 mA ≤ I
OUT
≤
+20 mA
Short-Circuit Current
5
40
40
mA
Load Impedance at Rails
6
25 25 Ω See Figure 20
Power-Up Time 2.5 2.5 µs Coming out of power-down
mode; V
DD
= 5 V
REFERENCE INPUT
Reference Current 90 90 µA V
REF
= V
DD
= 5.5 V, gain = 1
180 180 µA V
REF
= V
DD
= 5.5 V, gain = 2
Reference Input Range 1 V
DD
1 V
DD
V Gain = 1
1 V
DD
/2 1 V
DD
/2 V Gain = 2
Reference Input Impedance
16
16
kΩ
Gain = 2
32 32 kΩ Gain = 1