Datasheet

Data Sheet AD5696/AD5694
Rev. A | Page 17 of 24
SERIAL INTERFACE
The AD5696/AD5694 have a 2-wire, I
2
C-compatible serial
interface (see the I
2
C-Bus Specification, Version 2.1, January
2000, available from Philips Semiconductor). See Figure 2 for a
timing diagram of a typical write sequence. The AD5696/AD5694
can be connected to an I
2
C bus as slave devices, under the control
of a master device. The AD5696/AD5694 support standard
(100 kHz) and fast (400 kHz) data transfer modes. Support is
not provided for 10-bit addressing or general call addressing.
Input Shift Register
The input shift register of the AD5696/AD5694 is 24 bits wide.
Data is loaded into the device, MSB first, as a 24-bit word under
the control of the serial clock input, SCL. The first eight MSBs
make up the command byte (see Figure 35 and Figure 36).
• The first four bits of the command byte are the command
bits (C3, C2, C1, and C0), which control the mode of oper-
ation of the device (see Table 8).
• The last four bits of the command byte are the address bits
(DAC D, DAC C, DAC B, and DAC A), which select the
DAC that is operated on by the command (see Table 9).
The 8-bit command byte is followed by two data bytes, which
contain the data-word. For the AD5696, the data-word comprises
the 16-bit input code (see Figure 35); for the AD5694, the data-
word comprises the 12-bit input code followed by four don’t care
bits (see Figure 36). The data bits are transferred to the input
shift register on the 24 falling edges of SCL.
Commands can be executed on one DAC channel, any two or
three DAC channels, or on all four DAC channels, depending
on the address bits selected (see Table 9).
Table 8. Command Definitions
Command Bits
C3 C2 C1 C0 Command
0 0 0 0 No operation
0 0 0 1 Write to Input Register n (dependent
on
LDAC
)
0 0 1 0 Update DAC Register n with contents
of Input Register n
0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1 Hardware
LDAC
mask register
0 1 1 0 Software reset (power-on reset)
0
1
1
1
Reserved
1 X
1
X
1
X
1
Reserved
1
X = don’t care.
Table 9. Address Bits and Selected DACs
Address Bits
Selected DAC Channels
1
DAC D DAC C DAC B DAC A
0 0 0 1 DAC A
0 0 1 0 DAC B
0 0 1 1 DAC A and DAC B
0
1
0
0
DAC C
0 1 0 1 DAC A and DAC C
0 1 1 0 DAC B and DAC C
0 1 1 1 DAC A, DAC B, and DAC C
1 0 0 0 DAC D
1 0 0 1 DAC A and DAC D
… … … … …
1 1 1 1 All DACs
1
Any combination of DAC channels can be selected using the address bits.
Figure 35. Input Shift Register Contents, AD5696
Figure 36. Input Shift Register Contents, AD5694
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
C3
C2 C1 C0 DAC D DAC C DAC B DAC A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
D5 D4 D3 D2 D1 D0
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE
DATA HIGH BYTE DATA LOW BYTE
10799-302
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1
C0 DAC D DAC C DAC B DAC A D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
10799-300