Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LFCSP 16 WQ

Quad, 16-/12-Bit nanoDAC+

with I

C Interface

Data Sheet

AD5696/AD5694

Rev. A Document Feedback

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FEATURES

High relative accuracy (INL): ±2 LSB maximum at 16 bits

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User-selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

400 kHz I

C-compatible serial interface

4 I

C addresses available

Low glitch: 0.5 nV-sec

Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating

Low power: 1.8 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment

Programmable attenuators

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD5696 and AD5694, members of the nanoDAC+™ family,

are low power, quad, 16-/12-bit buffered voltage output DACs.

The devices include a gain select pin giving a full-scale output

of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from

a single 2.7 V to 5.5 V supply, are guaranteed monotonic by

design, and exhibit less than 0.1% FSR gain error and 1.5 mV

offset error performance. The devices are available in a 3 mm ×

3 mm LFCSP package and in a TSSOP package.

The AD5696/AD5694 incorporate a power-on reset circuit and a

RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power

up to zero scale or midscale and remain at that level until a valid

write takes place. The parts contain a per-channel power-down

feature that reduces the current consumption of the device in

power-down mode to 4 µA at 3 V.

The AD5696/AD5694 use a versatile 2-wire serial interface that

operates at clock rates up to 400 kHz and include a V

LOGIC

intended for 1.8 V/3 V/5 V logic.

Table 1. Quad nanoDAC+ Devices

Interface Reference 16-Bit 14-Bit 12-Bit

SPI Internal AD5686R AD5685R AD5684R

External AD5686 AD5684

C Internal AD5696R AD5695R AD5694R

External AD5696 AD5694

PRODUCT HIGHLIGHTS

1. High Relative Accuracy (INL).

AD5696 (16-bit): ±2 LSB maximum

AD5694 (12-bit): ±1 LSB maximum

2. Excellent DC Performance.

Total unadjusted error: ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP

16-lead TSSOP

SCL

LOGIC

SDA

INPUT

DAC

STRING

DAC A

BUFFER

OUT

INPUT

DAC

STRING

DAC B

BUFFER

OUT

INPUT

DAC

STRING

DAC C

BUFFER

OUT

INPUT

DAC

STRING

DAC D

BUFFER

OUT

REF

GNDV

POWER-

DOWN

LOGIC

POWER-ON

RESET

GAIN =

×1/×2

INTERFACE LOGIC

RSTSEL GAIN

LDAC RESET

AD5696/AD5694

10799-001

Summary of content (24 pages)

PAGE 1
Quad, 16-/12-Bit nanoDAC+ with I2C Interface AD5696/AD5694 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD High relative accuracy (INL): ±2 LSB maximum at 16 bits Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.
PAGE 2
AD5696/AD5694 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 17 Applications ....................................................................................... 1 Write and Update Commands .................................................. 18 Functional Block Diagram ....................................................
PAGE 3
Data Sheet AD5696/AD5694 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5696 Resolution Relative Accuracy Min A Grade Typ 16 Min B Grade Typ Max Unit ±1 ±1 ±2 ±3 ±1 Bits LSB LSB LSB ±1 ±1 Bits LSB LSB 16 ±2 ±2 ±8 ±8 ±1 ±0.12 ±2 ±1 ±0.12 4 ±4 ±0.2 ±0.2 ±0.25 ±0.25 0.4 +0.1 +0.01 ±0.02 ±0.
PAGE 4
AD5696/AD5694 Parameter LOGIC INPUTS3 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance LOGIC OUTPUTS (SDA)3 Output Low Voltage, VOL Output High Voltage, VOH Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD Data Sheet Min A Grade Typ Max Min B Grade Typ ±2 0.3 × VLOGIC 0.7 × VLOGIC Max Unit Test Conditions/Comments 1 ±2 0.3 × VLOGIC µA V V pF Per pin 0.4 V V pF ISINK = 3 mA ISOURCE = 3 mA 5.5 3 5.5 5.5 V µA V V 0.7 4 6 mA µA µA 0.
PAGE 5
Data Sheet AD5696/AD5694 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
PAGE 6
AD5696/AD5694 Data Sheet TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter1, 2 t1 t2 t3 t4 t5 t63 t7 t8 t9 t104 t114, 5 t12 t13 tSP6 CB 5 Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 20 + 0.1CB 20 400 0 Max 0.
PAGE 7
Data Sheet AD5696/AD5694 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 5. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This value was measured using a JEDEC standard 4-layer board with zero airflow. For the LFCSP package, the exposed pad must be tied to GND.
PAGE 8
AD5696/AD5694 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTA 1 12 A1 GAIN 8 LDAC 7 SDA 6 VOUTD 5 RESET 14 A1 13 SCL 12 A0 VOUTC 6 11 VLOGIC VOUTD 7 10 GAIN SDA 8 9 LDAC VDD 5 9 VLOGIC VOUTC 4 RSTSEL 15 GND 4 10 A0 VDD 3 16 VOUTA 3 11 SCL GND 2 VREF 1 VOUTB 2 AD5696/ AD5694 TOP VIEW (Not to Scale) 10799-007 13 RESET 14 RSTSEL 16 VOUTB 15 VREF AD5696/AD5694 NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 10799-006 TOP VIEW (Not to Scale) Figure 3.
PAGE 9
Data Sheet AD5696/AD5694 1.0 8 0.8 6 0.6 4 0.4 2 0.2 0 –2 0 –0.2 –4 –0.4 –6 –0.6 VDD = 5V TA = 25°C REFERENCE = 2.5V –0.8 30000 40000 50000 60000 CODE –1.0 0 625 8 6 6 4 4 ERROR (LSB) 8 2 0 –2 2 3750 4096 DNL –6 –6 –8 3125 3750 4096 INL –2 –4 CODE VDD = 5V TA = 25°C REFERENCE = 2.5V –10 –40 10 60 110 TEMPERATURE (°C) Figure 6. AD5694 INL Figure 9. INL Error and DNL Error vs. Temperature 10 0.8 8 0.6 6 0.4 4 ERROR (LSB) 1.0 0.2 0 –0.
PAGE 10
Data Sheet 10 0.10 8 0.08 6 0.06 4 0.04 ERROR (% of FSR) 2 INL 0 DNL –2 –4 –6 0.02 GAIN ERROR 0 FULL-SCALE ERROR –0.02 –0.04 –0.06 4.2 4.7 VDD = 5V –0.08 T = 25°C A REFERENCE = 2.5V –0.10 2.7 3.2 3.7 10799-126 VDD = 5V –8 TA = 25°C REFERENCE = 2.5V –10 3.2 3.7 2.7 5.2 SUPPLY VOLTAGE (V) 4.2 4.7 10799-129 ERROR (LSB) AD5696/AD5694 5.2 SUPPLY VOLTAGE (V) Figure 11. INL Error and DNL Error vs. Supply Voltage Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage 1.5 0.
PAGE 11
AD5696/AD5694 0.10 1.0 0.08 0.8 0.06 0.6 0.04 0.4 0.02 0.2 ΔVOUT (V) SINKING, 2.7V 0 –0.02 SINKING, 5V 0 –0.2 –0.04 –0.4 –0.06 –0.6 SOURCING, 5V SOURCING, 2.7V VDD = 5V –0.08 T = 25°C A REFERENCE = 2.5V –0.10 3.2 3.7 2.7 4.2 4.7 5.2 –1.0 SUPPLY VOLTAGE (V) 0 10 15 20 25 30 LOAD CURRENT (mA) Figure 17. TUE vs. Supply Voltage, Gain = 1 Figure 20. Headroom/Footroom vs. Load Current 7 0 VDD = 5V 6 TA = 25°C REFERENCE = 2.5V GAIN = 2 5 –0.01 –0.02 –0.
PAGE 12
AD5696/AD5694 Data Sheet 3 1.4 VOUTA VOUTB VOUTC VOUTD 1.2 2 VOUT (V) CURRENT (mA) 1.0 GAIN = 2 0.8 FULL-SCALE 0.6 GAIN = 1 1 0.4 10 60 110 TEMPERATURE (°C) 0 –5 0 5 10 TIME (µs) Figure 23. Supply Current vs. Temperature Figure 26. Exiting Power-Down to Midscale 4.0 3.5 VDD = 5V TA = 25°C REFERENCE = 2.5V 10799-143 0 –40 10799-140 0.2 2.5008 VOUTA VOUTB VOUTC VOUTD 3.0 2.5003 VOUT (V) VOUT (V) 2.5 2.0 2.4998 1.5 CHANNEL B TA = 25°C VDD = 5.25V REFERENCE = 2.
PAGE 13
Data Sheet AD5696/AD5694 4.0 T 0nF 0.1nF 0.22nF 4.7nF 10nF 3.9 3.8 VDD = 5V TA = 25°C REFERENCE = 2.5V VOUT (V) 3.7 1 3.6 3.5 3.4 3.3 3.2 VDD = 5V TA = 25°C REFERENCE = 2.5V 802mV BANDWIDTH (dB) –80 –100 –120 –140 FREQUENCY (Hz) 1.620 1.625 1.630 –20 –30 –40 –50 –160 10799-149 THD (dBV) –60 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 1.615 –10 –40 0 1.610 0 –20 –180 1.605 Figure 31. Settling Time vs. Capacitive Load VDD = 5V TA = 25°C REFERENCE = 2.5V 0 1.
PAGE 14
AD5696/AD5694 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 5 and Figure 6 show typical INL vs. code plots. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 15
Data Sheet AD5696/AD5694 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC in response to a digital code change and subsequent analog output change of another DAC. It is measured by loading one channel with a full-scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at midscale. The energy of the glitch is expressed in nV-sec.
PAGE 16
AD5696/AD5694 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5696/AD5694 are quad, 16-/12-bit, serial input, voltage output DACs that operate from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5696/AD5694 in a 24-bit word format via a 2-wire serial interface. The AD5696/AD5694 incorporate a power-on reset circuit to ensure that the DAC output powers up to a known output state. The devices also have a software powerdown mode that reduces the current consumption to 4 µA.
PAGE 17
Data Sheet AD5696/AD5694 SERIAL INTERFACE Table 8. Command Definitions The AD5696/AD5694 have a 2-wire, I2C-compatible serial interface (see the I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). See Figure 2 for a timing diagram of a typical write sequence. The AD5696/AD5694 can be connected to an I2C bus as slave devices, under the control of a master device. The AD5696/AD5694 support standard (100 kHz) and fast (400 kHz) data transfer modes.
PAGE 18
AD5696/AD5694 Data Sheet WRITE AND UPDATE COMMANDS SERIAL OPERATION For more information about the LDAC function, see the Load DAC (Hardware LDAC Pin) section. The 2-wire I2C serial bus protocol operates as follows: 1. Write to Input Register n (Dependent on LDAC) Command 0001 allows the user to write to each DAC’s dedicated input register individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC mask register). 2.
PAGE 19
Data Sheet AD5696/AD5694 READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5696/AD5694, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which determines both the read command that is to follow and the pointer address to read from; the command byte is also acknowledged by the DAC.
PAGE 20
AD5696/AD5694 Data Sheet POWER-DOWN OPERATION Table 11. Modes of Operation PDx1 0 PDx0 0 0 1 1 1 0 1 POWER-DOWN CIRCUITRY VOUTX RESISTOR NETWORK Figure 39. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC registers are unaffected in power-down mode, and the DAC registers can be updated while the device is in power-down mode.
PAGE 21
Data Sheet AD5696/AD5694 Table 13. LDAC Overwrite Definition Instantaneous DAC Updating (LDAC Held Low) Load LDAC Register For instantaneous updating of the DACs, LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the 24th clock, and the output begins to change (see Table 14).
PAGE 22
AD5696/AD5694 Data Sheet APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5696/AD5694 is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal.
PAGE 23
Data Sheet AD5696/AD5694 OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E PIN 1 INDICATOR 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 44.
PAGE 24
AD5696/AD5694 Data Sheet ORDERING GUIDE Model 1 AD5696ACPZ-RL7 AD5696BCPZ-RL7 AD5696ARUZ AD5696ARUZ-RL7 AD5696BRUZ AD5696BRUZ-RL7 AD5694BCPZ-RL7 AD5694ARUZ AD5694ARUZ-RL7 AD5694BRUZ AD5694BRUZ-RL7 EVAL-AD5696RSDZ EVAL-AD5694RSDZ 1 Resolution 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 12 Bits 12 Bits 12 Bits 12 Bits 12 Bits Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C