Datasheet
Table Of Contents
- Features
- Applications
- Functional Block Diagram
- General Description
- Product Highlights
- Table of Contents
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Theory of Operation
- Digital-to-Analog Converters
- Transfer Function
- DAC Architecture
- Serial Interface
- Standalone Operation
- Write and Update Commands
- Daisy-Chain Operation
- Readback Operation
- Power-Down Operation
- Load DAC (Hardware /LDAC Pin)
- Mask Register
- Hardware Reset (/RESET)
- Reset Select Pin (RSTSEL)
- Internal Reference Setup
- Solder Heat Reflow
- Long-Term Temperature Drift
- Thermal Hysteresis
- Applications Information
- Outline Dimensions

AD5689R/AD5687R Data Sheet
Rev. 0 | Page 4 of 28
A Grade
1
B Grade
1
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
REFERENCE OUTPUT
Output Voltage
7
2.4975
2.5025
2.4975
2.5025
V
At ambient
Reference Temperature
Coefficient
8, 9
5 20 2 5 ppm/°C See the Terminology section
Output Impedance
3
0.04 0.04 Ω
Output Voltage Noise
3
12 12 µV p-p 0.1 Hz to 10 Hz
Output Voltage Noise
Density
3
240 240 nV/√Hz At ambient; f = 10 kHz,
C
L
= 10 nF
Load Regulation Sourcing
3
20
20
µ
V/mA
At ambient
Load Regulation Sinking
3
40
40
µ
V/mA
At ambient
Output Current Load
Capability
3
±5
±5
mA V
DD
≥ 3 V
Line Regulation
3
100
100
µV/V
At ambient
Long-Term Stability/Drift
3
12 12 ppm After 1000 hours at 125°C
Thermal Hysteresis
3
125 125 ppm First cycle
25 25 ppm Additional cycles
LOGIC INPUTS
3
Input Current ±2 ±2 µA Per pin
Input Low Voltage (V
INL
) 0.3 × V
LOGIC
0.3 × V
LOGIC
V
Input High Voltage (V
INH
) 0.7 × V
LOGIC
0.7 × V
LOGIC
V
Pin Capacitance 2 2 pF
LOGIC OUTPUTS (SDO)
3
Output Low Voltage (V
OL
) 0.4 0.4 V
I
SINK
= 200
μ
A
Output High Voltage (V
OH
) V
LOGIC
− 0.4 V
LOGIC
− 0.4 V
I
SOURCE
= 200
μ
A
Floating State Output
Capacitance
4 4 pF
POWER REQUIREMENTS
V
LOGIC
1.8 5.5 1.8 5.5 V
I
LOGIC
3 3
µA
V
DD
2.7 5.5 2.7 5.5 V Gain = 1
V
DD
V
REF
+ 1.5 5.5 V
REF
+ 1.5 5.5 V Gain = 2
I
DD
V
IH
= V
DD
, V
IL
= GND,
V
DD
= 2.7 V to 5.5 V
Normal Mode
10
0.59 0.7 0.59 0.7 mA Internal reference off
1.1 1.3 1.1 1.3 mA Internal reference on,
at full scale
All Power-Down
Modes
11
1 4 1 4 µA −40°C to +85°C
6 6 µA −40°C to +105°C
1
Temperature range for A and B grades: −40°C to +105°C.
2
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV; it exists only when V
REF
= V
DD
with gain = 1 or when
V
REF
/2 = V
DD
with gain = 2. Linearity is calculated using a reduced code range of 256 to 65,280 (AD5689R) and 12 to 4080 (AD5687R).
3
Guaranteed by design and characterization; not production tested.
4
Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA, up to a junction temperature of 110°C.
5
V
DD
= 5 V. The devices include current limiting that is intended to protect them during temporary overload conditions. Junction temperature may be exceeded
during current limit, but operation above the specified maximum operation junction temperature can impair device reliability.
6
When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25
Ω × 1
mA = 25 mV (see
Fi
gure 32).
7
Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.
8
Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
9
Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
10
Interface inactive. Both DACs active. DAC outputs unloaded.
11
Both DACs powered down.