Datasheet

Data Sheet AD5689R/AD5687R
Rev. 0 | Page 3 of 28
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V; 1.8 V ≤ V
LOGIC
≤ 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. R
L
= 2 kΩ; C
L
= 200 pF.
Table 2.
A Grade
1
B Grade
1
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
2
AD5689R
Resolution 16 16 Bits
Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2
±2 ±8 ±1 ±3 Gain = 1
Differential
Nonlinearity
±1 ±1 LSB Guaranteed monotonic by design
AD5687R
Resolution
12
12
Bits
Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB
Differential
Nonlinearity
±1 ±1 LSB Guaranteed monotonic by design
Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register
Offset Error
+0.1
±4
+0.1
±1.5
mV
Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of FSR All 1s loaded to DAC register
Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR
Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1 % of FSR External reference; gain = 2; TSSOP
±0.25 ±0.2 % of FSR Internal reference; gain = 1; TSSOP
Offset Error Drift
3
±1 ±1 µV/°C
Gain Temperature
Coefficient
3
±1 ±1 ppm Of FSR/°C
DC Power Supply
Rejection Ratio
3
0.15
0.15
mV/V
DAC code = midscale;
V
DD
= 5 V ± 10%
DC Crosstalk
3
±2 ±2 µV Due to single channel, full-scale
output change
±3 ±3 µV/mA Due to load current change
±2 ±2 µV Due to powering down
(per channel)
OUTPUT CHARACTERISTICS
3
Output Voltage Range 0 V
REF
0 V
REF
V Gain = 1
0 2 × V
REF
0 2 × V
REF
V Gain = 2, see Figure 32
Capacitive Load Stability 2 2 nF R
L
= ∞
10 10 nF R
L
= 1 kΩ
Resistive Load
4
1 1 kΩ
Load Regulation 80 80 µV/mA 5 V ± 10%, DAC code = midscale;
−30 mA ≤ I
OUT
≤ 30 mA
80 80 µV/mA 3 V ± 10%, DAC code = midscale;
−20 mA ≤ I
OUT
≤ 20 mA
Short-Circuit Current
5
40 40 mA
Load Impedance at Rails
6
25
25
Ω
See Figure 32
Power-Up Time 2.5 2.5 µs Coming out of power-down
mode; V
DD
= 5 V