Datasheet

AD5689R/AD5687R Data Sheet
Rev. 0 | Page 20 of 28
SERIAL INTERFACE
The AD5689R/AD5687R have a 3-wire serial interface
(
SYNC
, SCLK, and SDIN) that is compatible with SPI, QSPI™,
and MICROWIRE® interface standards as well as most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The AD5689R
/AD5687R contain an SDO pin that allows
the user to daisy-chain multiple devices together (see the
Daisy-Chain Operation section) or read back data.
Input Shift Register
The input shift register of the AD5689R/AD5687R is 24 bits
wide, and data is loaded MSB first (DB23). The first four bits
are the command bits, C3 to C0 (see Table 9), followed by
the 4-bit DAC address bits, composed of DAC B, DAC A,
and two don’t care bits that must be set to 0 (see Table 8).
Finally, the data-word completes the input shift register.
The data-word comprises 16-bit or 12-bit input code, followed
by zero don’t care bits (for the AD5689R) or four don’t care bits
(for the AD5687R), as shown in Figure 44 and Figure 45, respec-
tively). These data bits are transferred to the input shift register
on the 24 falling edges of SCLK and updated on the rising edge
of
SYNC
.
Commands can be executed on individual DAC channels or on
both DAC channels, depending on the address bits selected.
Table 8. Address Commands
Address (n)
Selected DAC Channel
DAC B
0 0
DAC A
0 0 0 1 DAC A
1 0 0 0 DAC B
1 0 0 1 DAC A and DAC B
Table 9. Command Definitions
Command
C3 C2 C1 C0 Description
0 0 0 0 No operation
0 0 0 1 Write to Input Register n (dependent on
LDAC
)
0 0 1 0 Update DAC Register n with contents of Input Register n
0
0
1
1
Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1 Hardware
LDAC
mask register
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Internal reference setup register
1 0 0 0 Set up DCEN register (daisy-chain enable)
1 0 0 1 Set up readback register (readback enable)
1 0 1 0 Reserved
… … … … Reserved
1 1 1 1 Reserved
Figure 44. AD5689R Input Shift Register Content
Figure 45. AD5687R Input Shift Register Content
ADDRESS BITS COMMAND BITS
DAC
B
0 0
DAC
A
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
11256-045
DAC
B
DAC
A
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS BITS COMMAND BITS
0 0
X X X X
C3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
11256-046