Datasheet

Data Sheet AD5689/AD5687
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 2.
V
DD
= 2.7 V to 5.5 V, 1.8 V ≤ V
LOGIC
≤ 5.5 V; V
REF
= 2.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
1.8 V ≤ V
LOGIC
< 2.7 V 2.7 V ≤ V
LOGIC
≤ 5.5 V
Parameter
1
Min Max Min Max Unit Description
t
1
33 20 ns SCLK cycle time
t
2
16 10 ns SCLK high time
t
3
16 10 ns SCLK low time
t
4
15 10 ns
SYNC
to SCLK falling edge setup time
t
5
5 5 ns Data setup time
t
6
5 5 ns Data hold time
t
7
15 10 ns SCLK falling edge to
SYNC
rising edge
t
8
20
20
ns
Minimum
SYNC
high time (update single channel or both channels)
t
9
16 10 ns
SYNC
falling edge to SCLK fall ignore
t
10
25 15 ns
LDAC
pulse width low
t
11
30 20 ns SCLK falling edge to
LDAC
rising edge
t
12
20 20 ns SCLK falling edge to
LDAC
falling edge
t
13
30 30 ns
RESET
minimum pulse width low
t
14
30 30 ns
RESET
pulse activation time
Power-Up Time 4.5 4.5 µs Time that is required to exit power-down mode and enter
normal mode of operation; 24
th
clock edge to 90% of DAC
midscale value with output unloaded
1
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V, 2.7 V ≤ V
LOGIC
≤ V
DD
. Guaranteed by design and characterization; not production tested.
Figure 2. Serial Write Operation
t
4
t
3
SCLK
SYNC
SDIN
t
1
t
2
t
5
t
6
t
7
t
8
DB23
t
9
t
10
t
11
LDAC
1
LDAC
2
t
12
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
RESET
t
13
t
14
V
OUT
X
DB0
11255-002