Datasheet

Data Sheet AD5689/AD5687
Rev. 0 | Page 9 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
LFCSP TSSOP
1 3 V
OUT
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 4 GND Ground Reference Point for All Circuitry on the AD5689/AD5687.
3 5 V
DD
Power Supply Input. The AD5689/AD5687 can be operated from 2.7 V to 5.5 V. Decouple the supply
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 2 NC No Connect. Do not connect to this pin.
5 7 V
OUT
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
6 8 SDO Serial Data Output. SDO can be used to daisy-chain a number of AD5689/AD5687 devices together,
or it can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid
on the falling edge of the clock.
7 9
LDAC LDAC
can be operated in two modes: asynchronous and synchronous. Pulsing this pin low allows
either or both DAC registers to be updated if the input registers have new data; both DAC outputs can
be updated simultaneously. This pin can also be tied permanently low.
8 10 GAIN Gain Select. When this pin is tied to GND, both DACs output a span from 0 V to V
REF
. If this pin is tied
to V
LOGIC
, both DACs output a span of 0 V to 2 × V
REF
.
9 11 V
LOGIC
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
11 13
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
12
14
SDIN
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
13 15
RESET
Asynchronous Reset Input. The
RESET
input is falling edge sensitive. When
RESET
is low, all
LDAC
pulses are ignored. When
RESET
is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
14 16 RSTSEL
Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to
V
LOGIC
powers up both DACs to midscale.
15 1 V
REF
Reference Input Voltage.
16 6 NC No Connect. Do not connect to this pin.
17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.
12
11
10
1
3
4
SDIN
SYNC
SCLK
9
V
LOGIC
V
OUT
A
V
DD
2
GND
NC
6
SDO
5
V
OUT
B
7
LDAC
8
GAIN
16
NC
15
V
REF
14
RSTSEL
13
RESET
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
2. THE EXPOSED PAD MUST BE TIED TO GND.
TOP VIEW
(Not to Scale)
AD5689/
AD5687
11255-006
1
2
3
4
5
6
7
8
NC
V
OUT
A
GND
V
OUT
B
NC
V
DD
V
REF
SDO
16
15
14
13
12
11
10
9
RESET
SDIN
SYNC
GAIN
LDAC
V
LOGIC
SCLK
RSTSEL
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
TOP VIEW
(Not to Scale)
AD5689/
AD5687
11255-007