Datasheet

Data Sheet AD5689/AD5687
Rev. 0 | Page 3 of 24
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V; 1.8 V ≤ V
LOGIC
≤ 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. R
L
= 2 kΩ; C
L
= 200 pF.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
1
AD5689
Resolution 16 Bits
Relative Accuracy ±1 ±2 LSB Gain = 2
±1 ±3 Gain = 1
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5687
Resolution 12 Bits
Relative Accuracy ±0.12 ±1 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register
Offset Error +0.1 ±1.5 mV
Full-Scale Error +0.01 ±0.1 % of FSR All 1s loaded to DAC register
Gain Error ±0.02 ±0.1 % of FSR
Total Unadjusted Error ±0.01 ±0.1 % of FSR Gain = 2; TSSOP
±0.2 % of FSR Gain = 1; TSSOP
Offset Error Drift
2
±1 µV/°C
Gain Temperature Coefficient
2
±1 ppm Of FSR/°C
DC Power Supply Rejection Ratio
2
0.15 mV/V DAC code = midscale, V
DD
= 5 V ± 10%
DC Crosstalk
2
±2 µV Due to single-channel, full-scale output change
±3 µV/mA Due to load current change
±2 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS
2
Output Voltage Range 0 V
REF
V Gain = 1
0 2 × V
REF
V Gain = 2; see Figure 23
Capacitive Load Stability 2 nF R
L
= ∞
10 nF R
L
= 1 kΩ
Resistive Load
3
1 kΩ
Load Regulation 80 µV/mA 5 V ± 10%, DAC code = midscale;
−30 mA ≤ I
OUT
≤ 30 mA
80
µV/mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ I
OUT
≤ 20 mA
Short-Circuit Current
4
40 mA
Load Impedance at Rails
5
25 Ω See Figure 23
Power-Up Time 2.5 µs Coming out of power-down mode; V
DD
= 5 V
REFERENCE INPUT
Reference Current
6
90 µA V
REF
= V
DD
= V
LOGIC
=5.5 V, gain = 1
180 µA V
REF
= V
DD
= V
LOGIC
=5.5 V, gain = 2
Reference Input Range 1 V
DD
V Gain = 1
1
V
DD
/2
V
Gain = 2
Reference Input Impedance 16 kΩ Gain = 1
32 kΩ Gain = 2
LOGIC INPUTS
2
Input Current ±2 µA Per pin
Input Low Voltage (V
INL
) 0.3 × V
LOGIC
V
Input High Voltage (V
INH
) 0.7 × V
LOGIC
V
Pin Capacitance 2 pF