Datasheet

AD5689/AD5687 Data Sheet
Rev. 0 | Page 20 of 24
READBACK OPERATION
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy-
chain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one of
the address bits, DAC B or DAC A, selects the register to be read.
Note that only one DAC register can be selected during readback.
The remaining three address bits (which include the two don’t
care bits) must be set to Logic 0. The remaining data bits in the
write sequence are ignored. If more than one address bit is
selected or no address bit is selected, DAC Channel A is read
back by default. During the next SPI write, the data that appears
on the SDO output contains the data from the previously
addressed register.
For example, to read back the DAC register for Channel A,
implement the following sequence:
1. Write 0x900000 to the AD5689/AD5687 input register. This
setting configures the part for read mode with the Channel A
DAC register selected. Note that all data bits, DB15 to DB0,
are don’t care bits.
2. Follow this write operation with a second write, a NOP
condition, 0x000000. During this write, the data from the
register is clocked out on the SDO line. DB23 to DB20
contain undefined data, and the last 16 bits contain the
DB19 to DB4 DAC register contents.
POWER-DOWN OPERATION
The AD5689/AD5687 contain three separate power-down modes.
Command 0100 controls the power-down function (see Table 9).
These power-down modes are software-programmable by
setting eight bits, Bit DB7 to Bit DB0, in the input shift register.
There are two bits associated with each DAC channel. Table 11
explains how the state of the two bits corresponds to the mode
of operation of the device.
Either or both DACs (DAC B, DAC A) can be powered down to
the selected mode by setting the corresponding bits. See Table 12
for the contents of the input shift register during the power-down/
power-up operation.
Table 11. Modes of Operation
Operating Mode PDx1 PDx0
Normal Operation Mode 0 0
Power-Down Modes
1 kΩ to GND 0 1
100 kΩ to GND 1 0
Three-State 1 1
When both Bit PDx1 and Bit PDx0 (where x is the channel that is
selected) in the input shift register are set to 0, the parts work
normally, with a normal power consumption of 4 mA at 5 V.
However, for the three power-down modes of the AD5689/
AD5687, the supply current falls to 4 μA at 5 V. Not only does
the supply current fall, but the output stage is also internally
switched from the output of the amplifier to a resistor network
of known values. This switchover has the advantage that the
output impedance of the part is known while the part is in
power-down mode. The three power-down options are as follows:
• The output is connected internally to GND through a 1 kΩ
resistor.
• The output is connected internally to GND through a 100 kΩ
resistor.
• The output is left open-circuited (three-state).
The output stage is illustrated in Figure 41.
Figure 41. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down, and the DAC register can
be updated while the device is in power-down mode. The time
that is required to exit power-down is typically 4.5 µs for V
DD
= 5 V
Table 12. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
1
DB23
(MSB)
DB22 DB21 DB20 DB19 to DB16 DB15 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0
(LSB)
0 1 0 0 X X PDB1 PDB0 1 1 1 1 PDA1 PDA0
Command bits (C3 to C0) Address bits; don’t care Power-down,
select DAC B
Set to 1 Set to 1 Power-down,
select DAC A
1
X = don’t care.
RESISTOR
NETWORK
V
OUT
X
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
11255-041