Datasheet

Data Sheet AD5686R/AD5685R/AD5684R
Rev. B | Page 21 of 32
SERIAL INTERFACE
The AD5686R/AD5685R/AD5684R have a 3-wire serial
interface (
SYNC
, SCLK, and SDIN) that is compatible with
SPI, QSPI, and MICROWIRE interface standards as well as
most DSPs. See Figure 2 for a timing diagram of a typical
write sequence. The AD5686R/AD5685R/AD5684R contain
an SDO pin to allow the user to daisy-chain multiple devices
together (see the Daisy-Chain Operation section) or for
readback.
Input Shift Register
The input shift register of the AD5686R/AD5685R/AD5684R is
24 bits wide. Data is loaded MSB first (DB23) and the first four
bits are the command bits, C3 to C0 (see Table 7), followed by
the 4-bit DAC address bits, DAC A, DAC B, DAC C, DAC D
(see Table 8), and finally the bit data-word.
The data-word comprises 16-bit, 14-bit, or 12-bit input code,
followed by zero, two or four don’t care bits for the AD5686R,
AD5685R, and AD5684R, respectively (see Figure 51, Figure 52,
and Figure 53). These data bits are transferred to the input
register on the 24 falling edges of SCLK and are updated on the
rising edge of
SYNC
.
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DACs, depending on the
address bits selected.
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
0
0
0
0
No operation
0
0
0
1
Write to Input Register n (dependent on
LDAC
)
0 0 1 0
Update DAC Register n with contents of Input
Register n
0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1
Hardware
LDAC
mask register
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Internal reference setup register
1 0 0 0 Set up DCEN register (daisy-chain enable)
1 0 0 1 Set up readback register (readback enable)
1 0 1 0 Reserved
… … … … Reserved
1 1 1 1 Reserved
Table 8. Address Commands
Address (n)
Selected DAC Channel
1
DAC D
DAC C
DAC B
DAC A
0 0 0 1 DAC A
0 0 1 0 DAC B
0 1 0 0 DAC C
1
0
0
0
DAC D
0 0 1 1 DAC A and DAC B
1 1 1 1 All DACs
1
Any combination of DAC channels can be selected using the address bits.
Figure 51. AD5686R Input Shift Register Content
Figure 52. AD5685R Input Shift Register Content
Figure 53. AD5684R Input Shift Register Content
ADDRESS BITSCOMMAND BITS
DAC
D
DAC
C
DAC
B
DAC
A
D15 D14 D13 D12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1 D0C3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
10485-054
ADDRESS BITSCOMMAND BITS
DAC
D
DAC
C
DAC
B
DAC
A
D13 D12 D11 D10 D9
D8 D7 D6 D5 D4 D3 D2
D1 D0 X XC3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
10485-055
ADDRESS BITSCOMMAND BITS
DAC
D
DAC
C
DAC
B
DAC
A
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
C3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
10485-056