Datasheet

AD5686R/AD5685R/AD5684R Data Sheet
Rev. B | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description LFCSP TSSOP
1 3 V
OUT
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 4 GND Ground Reference Point for All Circuitry on the Part.
3 5 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 6 V
OUT
C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5 7 V
OUT
D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5686R/AD5685R/AD5684R devices
together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is
valid on the falling edge of the clock.
7 9
LDAC LDAC
can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to simultaneously update. This pin can also be tied permanently low.
8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to V
REF
. If this
pin is tied to V
LOGIC
, all four DACs output a span of 0 V to 2 × V
REF
.
9 11 V
LOGIC
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
11 13
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
12
14
SDIN
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
13 15
RESET
Asynchronous Reset Input. The
RESET
input is falling edge sensitive. When
RESET
is low, all
LDAC
pulses are ignored. When
RESET
is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
14 16 RSTSEL
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
V
LOGIC
powers up all four DACs to midscale.
15 1 V
REF
Reference Voltage. The AD5686R/AD5685R/AD5684R have a common reference pin. When using
the internal reference, this is the reference output pin. When using an external reference, this is the
reference input pin. The default for this pin is as a reference output.
16 2 V
OUT
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.
12
11
10
1
3
4
SDIN
SYNC
SCLK
9
V
LOGIC
V
OUT
A
V
DD
2
GND
V
OUT
C
6
SDO
5
V
OUT
D
7
LDAC
8
GAIN
16
V
OUT
B
15
V
REF
14
RSTSEL
13
RESET
AD5686R/AD5685R/AD5684R
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
TOP VIEW
(Not to Scale)
10485-006
1
2
3
4
5
6
7
8
V
OUT
B
V
OUT
A
GND
V
OUT
D
V
OUT
C
V
DD
V
REF
SDO
16
15
14
13
12
11
10
9
RESET
SDIN
SYNC
GAIN
LDAC
V
LOGIC
SCLK
RSTSEL
TOP VIEW
(Not to Scale)
AD5686R/
AD5685R/
AD5684R
10485-007