Datasheet

Data Sheet AD5686/AD5684
Rev. A | Page 7 of 28
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 4
and Figure 5. V
DD
= 2.7 V to 5.5 V, 1.8 V ≤ V
LOGIC
≤ 5.5 V; V
REF
= 2.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
1.8 V ≤ V
LOGIC
< 2.7 V 2.7 V ≤ V
LOGIC
≤ 5.5 V
Parameter
1
Symbol Min Max Min Max Unit
SCLK Cycle Time t
1
66 40 ns
SCLK High Time t
2
33 20 ns
SCLK Low Time t
3
33 20 ns
SYNC
to SCLK Falling Edge t
4
33 20 ns
Data Setup Time t
5
5 5 ns
Data Hold Time t
6
5 5 ns
SCLK Falling Edge to
SYNC
Rising Edge t
7
15 10 ns
Minimum
SYNC
High Time t
8
60 30 ns
Minimum
SYNC
High Time t
9
60 30 ns
SDO Data Valid from SCLK Rising Edge t
10
36 25 ns
SCLK Falling Edge to
SYNC
Rising Edge t
11
15 10 ns
SYNC
Rising Edge to SCLK Rising Edge t
12
15 10 ns
1
Maximum SCLK frequency is 25 MHz or 15 MHz at V
DD
= 2.7 V to 5.5 V, 1.8 V ≤ V
LOGIC
≤ V
DD
. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Figure 4. Daisy-Chain Timing Diagram
200µA I
OL
200µA I
OH
V
OH
(MIN)
TO OUTPUT
PIN
C
L
20pF
10797-003
t
4
t
5
t
6
t
8
S
DO
SDIN
SYNC
SCLK
4824
DB23 DB0 DB23 DB0
DB23
INPUT WORD FOR DAC NUNDEFINED
INPUT WORD FOR DAC N + 1INPUT WORD FOR DAC N
DB0
t
11
t
12
t
10
10797-004