Datasheet

AD5686/AD5684 Data Sheet
Rev. A | Page 6 of 28
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 2.
V
DD
= 2.7 V to 5.5 V, 1.8 V ≤ V
LOGIC
≤ 5.5 V; V
REF
= 2.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
1.8 V ≤ V
LOGIC
< 2.7 V 2.7 V ≤ V
LOGIC
≤ 5.5 V
Parameter
1
Symbol Min Max Min Max Unit
SCLK Cycle Time t
1
33 20 ns
SCLK High Time t
2
16 10 ns
SCLK Low Time t
3
16 10 ns
SYNC to SCLK Falling Edge Setup Time
t
4
15 10 ns
Data Setup Time t
5
8 5 ns
Data Hold Time t
6
8 5 ns
SCLK Falling Edge to SYNC Rising Edge
t
7
15 10 ns
Minimum SYNC High Time
t
8
20 20 ns
SYNC Falling Edge to SCLK Fall Ignore
t
9
16 10 ns
LDAC Pulse Width Low
t
10
25 15 ns
SCLK Falling Edge to LDAC Rising Edge
t
11
30 20 ns
SCLK Falling Edge to LDAC Falling Edge
t
12
20 20 ns
RESET Minimum Pulse Width Low
t
13
30 30 ns
RESET Pulse Activation Time
t
14
30 30 ns
Power-Up Time
2
4.5 4.5 μs
1
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V, 1.8 V ≤ V
LOGIC
≤ V
DD
. Guaranteed by design and characterization; not production tested.
2
Time to exit power-down to normal mode of AD5686/AD5684 operation, 32
nd
clock edge to 90% of DAC midscale value, with output unloaded.
Figure 2. Serial Write Operation
t
4
t
3
SCLK
SYNC
SDIN
t
1
t
2
t
5
t
6
t
7
t
8
DB23
t
9
t
10
t
11
LDAC
1
LDAC
2
t
12
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
RESET
t
13
t
14
V
OUT
DB0
10797-002