Datasheet

AD5686/AD5684 Data Sheet
Rev. A | Page 22 of 28
LOAD DAC (HARDWARE LDAC PIN)
The AD5686/AD5684 DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC register are controlled by the
LDAC
pin.
Figure 42. Simplified Diagram of Input Loading Circuitry for a Single DAC
Instantaneous DAC Updating (
LDAC
Held Low)
LDAC
is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the rising edge of
SYNC
and
the output begins to change (see Table 14).
Deferred DAC Updating (
LDAC
Is Pulsed Low)
LDAC
is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
updated by taking
LDAC
low after
SYNC
has been taken
high. The update now occurs on the falling edge of
LDAC
.
LDAC MASK REGISTER
Command 0101 is reserved for the software
LDAC
function.
Address bits are ignored. Writing to the DAC using Command
0101 loads the 4-bit
LDAC
register (DB3 to DB0). The default
for each channel is 0; that is, the
LDAC
pin works normally.
Setting the bits to 1 forces this DAC channel to ignore transitions
on the
LDAC
pin, regardless of the state of the hardware
LDAC
pin. This flexibility is useful in applications where the user
wishes to select which channels respond to the
LDAC
pin.
The
LDAC
register gives the user extra flexibility and control
over the hardware
LDAC
pin (see Table 13). Setting the
LDAC
bits (DB3 to DB0) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware
LDAC
pin.
Table 13.
LDAC
Overwrite Definition
Load
LDAC
Register
LDAC
Bits
(DB3 to DB0)
LDAC
Pin
LDAC
Operation
0 1 or 0
Determined by the LDAC
pin.
1 X
1
DAC channels are updated and
override the LDAC
pin. DAC
channels see LDAC
as 1.
1
X = don’t care.
Table 14. Write Commands and
LDAC
Pin Truth Table
1
Command Description
Hardware
LDAC
Pin State
Input Register
Contents DAC Register Contents
0001
Write to Input Register n (dependent on
LDAC
)
V
LOGIC
Data update No change (no update)
GND
2
Data update Data update
0010 Update DAC Register n with contents of Input
Register n
V
LOGIC
No change Updated with input register contents
GND No change Updated with input register contents
0011 Write to and update DAC Channel n V
LOGIC
Data update Data update
GND Data update Data update
1
A high to low hardware
LDAC
pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
(blocked) by the
LDAC
mask register.
2
When LDAC is permanently tied low, the LDAC mask bits are ignored.
SYNC
SCLK
V
OUT
X
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
AMPLIFIER
LDAC
SDO
SDIN
V
REF
INPUT
REGISTER
16-/12-BIT
DAC
10797-059