Datasheet

AD5686/AD5684 Data Sheet
Rev. A | Page 18 of 28
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5686/AD5684 are quad, 16-/12-bit, serial input, voltage
output DACs. The parts operate from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5686/AD5684 in a 24-bit word
format via a 3-wire serial interface. The AD5686/AD5684
incorporate a power-on reset circuit to ensure that the DAC
output powers up to a known output state. The devices also
have a software power-down mode that reduces the typical
current consumption to typically 4 µA.
TRANSFER FUNCTION
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by






×=
N
REF
OUT
D
GainVV
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows:
0 to 4095 for the 12-bit device.
0 to 65,535 for the 16-bit device.
N is the DAC resolution.
V
REF
is the value of the external reference.
Gain is the gain of the output amplifier and is set to 1 by default.
The gain can be set to ×1 or ×2 using the gain select pin. When
this pin is tied to GND, all four DAC outputs have a span of 0 V
to V
REF
. When this pin is tied to V
DD
, all four DAC outputs have
a span of 0 V to 2 × V
REF
.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 36 shows a block diagram of the DAC
architecture.
Figure 36. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 37. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because the DAC is a string of resistors,
it is guaranteed monotonic.
Figure 37. Resistor String Structure
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
DD
. The actual
range depends on the value of V
REF
, the GAIN pin, offset error,
and gain error. The GAIN pin selects the gain of the output.
• If this pin is tied to GND, all four outputs have a gain of 1,
and the output range is 0 V to V
REF
.
• If this pin is tied to V
DD
, all four outputs have a gain of 2,
and the output range is 0 V to 2 × V
REF
.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
REF (+)
V
REF
GND
REF (–)
V
OUT
X
GAIN
(GAIN = 1 OR 2)
10797-052
R
R
R
R
R
TO OUTPUT
AMPLIFIER
V
REF
10797-053