Datasheet

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Quad, 16-/12-Bit nanoDAC+

with SPI Interface

Data Sheet

AD5686/AD5684

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FEATURES

High relative accuracy (INL): ±2 LSB maximum @ 16 bits

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

50 MHz SPI with readback or daisy chain

Low glitch: 0.5 nV-sec

Robust 4 kV HBM and 1.5 kV FICDM ESD rating

Low power: 1.8 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment

Programmable attenuators

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD5686/AD5684, members of the nanoDAC+™ family, are

low power, quad, 16-/12-bit buffered voltage output DACs.

The devices include a gain select pin giving a full-scale output

of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from

a single 2.7 V to 5.5 V supply, are guaranteed monotonic by

design, and exhibit less than 0.1% FSR gain error and 1.5 mV

offset error performance. The devices are available in a 3 mm

× 3 mm LFCSP and a TSSOP package.

The AD5686/AD5684 also incorporate a power-on reset circuit

and a RSTSEL pin that ensures that the DAC outputs power up

to zero scale or midscale and remain at that level until a valid

write takes place. Each part contains a per-channel power-down

feature that reduces the current consumption of the device to

4 µA at 3 V while in power-down mode.

The AD5686/AD5684 employ a versatile SPI interface that

operates at clock rates up to 50 MHz, and all devices contain

a V

LOGIC

pin intended for 1.8 V/3 V/5 V logic.

Table 1. Quad nanoDAC+ Devices

Interface Reference 16-Bit 14-Bit 12-Bit

SPI Internal AD5686R AD5685R AD5684R

SPI External AD5686 AD5684

C Internal AD5696R AD5695R AD5694R

C External AD5696 AD5694

PRODUCT HIGHLIGHTS

1. High Relative Accuracy (INL).

AD5686 (16-bit): ±2 LSB maximum

AD5684 (12-bit): ±1 LSB maximum

2. Excellent DC Performance.

Total unadjusted error: ±0.1% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.1% of FSR maximum

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP

16-lead TSSOP

SCLK

LOGIC

SYNC

SDIN

SDO

INPUT

DAC

STRING

DAC A

BUFFER

OUT

INPUT

DAC

STRING

DAC B

BUFFER

OUT

INPUT

DAC

STRING

DAC C

BUFFER

OUT

INPUT

DAC

STRING

DAC D

BUFFER

OUT

REF

GNDV

POWER-

DOWN

LOGIC

POWER-ON

RESET

GAIN

×1/×2

INTERFACE LOGIC

RSTSEL

GAINLDAC RESET

AD5686/AD5684

10797-001

Summary of content (28 pages)

PAGE 1
Quad, 16-/12-Bit nanoDAC+ with SPI Interface AD5686/AD5684 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): ±2 LSB maximum @ 16 bits Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.
PAGE 2
AD5686/AD5684 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 19 Applications ....................................................................................... 1 Standalone Operation ................................................................ 20 Functional Block Diagram ...........................................
PAGE 3
Data Sheet AD5686/AD5684 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF. Table 2. Parameter STATIC PERFORMANCE 2 AD5686 Resolution Relative Accuracy Min A Grade 1 Typ Max 16 Min B Grade1 Typ Max Unit Test Conditions/Comments ±1 ±1 ±2 ±3 ±1 Bits LSB LSB LSB Gain = 2 Gain = 1 Guaranteed monotonic by design ±0.12 16 ±2 ±2 ±8 ±8 ±1 ±0.12 0.4 +0.1 +0.01 ±2 ±1 4 ±4 ±0.2 0.4 +0.1 +0.
PAGE 4
AD5686/AD5684 Parameter Data Sheet Min A Grade 1 Typ Max Min B Grade1 Typ Max Unit Test Conditions/Comments ±2 0.3 × VLOGIC µA V V pF Per pin 0.4 V V pF ISINK = 200 μA ISOURCE = 200 μA 5.5 3 5.5 5.5 V µA V V 0.7 4 6 mA µA µA 3 LOGIC INPUTS Input Current Input Low Voltage (VINL) Input High Voltage (VINH) Pin Capacitance LOGIC OUTPUTS (SDO)3 Output Low Voltage, VOL Output High Voltage, VOH Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD ±2 0.3 × VLOGIC 0.
PAGE 5
Data Sheet AD5686/AD5684 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 3.
PAGE 6
AD5686/AD5684 Data Sheet TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4.
PAGE 7
Data Sheet AD5686/AD5684 DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 5. 1.8 V ≤ VLOGIC < 2.
PAGE 8
AD5686/AD5684 Data Sheet t1 SCLK 24 1 t8 t4 t3 24 1 t7 t2 t9 SYNC t6 t5 DB23 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23 DB0 NOP CONDITION t10 DB0 DB23 UNDEFINED DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 5. Readback Timing Diagram Rev.
PAGE 9
Data Sheet AD5686/AD5684 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free (J-STD-020) ESD HBM 1 FICDM 1 Rating −0.3 V to +7 V −0.3 V to +7 V −0.
PAGE 10
AD5686/AD5684 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 13 RESET 14 RSTSEL 16 VOUTB 15 VREF AD5686/AD5684 VOUTA 1 11 SYNC VDD 3 10 SCLK 9 VLOGIC 16 RSTSEL VOUTB 2 15 RESET 14 SDIN 13 SYNC VOUTA 3 AD5686/ AD5684 GND 4 GAIN 8 LDAC 7 SDO 6 VOUTD 5 VOUTC 4 VREF 1 NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 10797-006 TOP VIEW (Not to Scale) Figure 6.
PAGE 11
Data Sheet AD5686/AD5684 1.0 8 0.8 6 0.6 4 0.4 2 0.2 0 –2 0 –0.2 –4 –0.4 –6 –0.6 V = 5V –8 DD TA = 25°C REFERENCE = 2.5V –10 0 10000 20000 VDD = 5V TA = 25°C REFERENCE = 2.5V –0.8 30000 40000 50000 60000 CODE –1.0 0 625 1250 3125 3750 4096 Figure 11. AD5684 DNL 10 10 8 8 6 6 4 4 ERROR (LSB) 2 0 –2 –4 2 INL 0 DNL –2 –4 –6 –6 0 625 1250 1875 2500 3125 3750 4096 CODE 0.8 8 0.6 6 0.4 4 ERROR (LSB) 10 0.2 0 –0.2 2 110 DNL –2 –4 –0.6 –6 V = 5V –0.
PAGE 12
Data Sheet 10 0.10 8 0.08 6 0.06 4 0.04 ERROR (% of FSR) 2 INL 0 DNL –2 –4 –6 GAIN ERROR 0 FULL-SCALE ERROR –0.02 –0.04 –0.06 VDD = 5V –0.08 T = 25°C A REFERENCE = 2.5V –0.10 2.7 3.2 3.7 VDD = 5V TA = 25°C REFERENCE = 2.5V –10 2.7 3.2 3.7 4.2 4.7 10797-126 –8 0.02 5.2 SUPPLY VOLTAGE (V) 4.2 4.7 10797-129 ERROR (LSB) AD5686/AD5684 5.2 SUPPLY VOLTAGE (V) Figure 14. INL Error and DNL Error vs. Supply Voltage Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage 1.5 0.
PAGE 13
AD5686/AD5684 0.10 1.0 0.08 0.8 0.06 0.6 0.04 0.4 0.02 0.2 0 –0.02 –0.2 –0.04 –0.4 –0.06 –0.6 V = 5V –0.08 T DD= 25°C A REFERENCE = 2.5V –0.10 2.7 3.2 3.7 SOURCING 5V SOURCING 2.7V –0.8 4.2 4.7 5.2 SUPPLY VOLTAGE (V) –1.0 0 5 10 15 20 25 30 LOAD CURRENT (mA) Figure 20. TUE vs. Supply Voltage, Gain = 1 Figure 23. Headroom/Footroom vs. Load Current 0 7 VDD = 5V 6 TA = 25°C GAIN = 2 REFERENCE = 2.5V 5 –0.01 –0.02 0xFFFF –0.03 4 0xC000 VOUT (V) –0.04 –0.05 –0.
PAGE 14
AD5686/AD5684 Data Sheet 3 CH A CH B CH C CH D SYNC 1.4 1.2 2 VOUT (V) CURRENT (mA) 1.0 0.8 0.6 GAIN = 2 FULL-SCALE GAIN = 1 1 0.4 10 60 0 –5 10797-140 0 –40 110 TEMPERATURE (°C) 5 10 TIME (µs) Figure 26. Supply Current vs. Temperature Figure 29. Exiting Power-Down to Midscale 2.5008 4.0 3.5 0 10797-143 VDD = 5V TA = 25°C REFERENCE = 2.5V 0.2 DAC A DAC B DAC C DAC D 3.0 2.5003 VOUT (V) VOUT (V) 2.5 2.0 2.4998 1.5 CHANNEL B TA = 25°C VDD = 5.25V REFERENCE = 2.
PAGE 15
Data Sheet AD5686/AD5684 4.0 T 0nF 0.1nF 10nF 0.22nF 4.7nF 3.9 3.8 VDD = 5V TA = 25°C REFERENCE = 2.5V VOUT (V) 3.7 1 3.6 3.5 3.4 3.3 3.2 VDD = 5V TA = 25°C REFERENCE = 2.5V 802mV BANDWIDTH (dB) –80 –100 –120 –140 FREQUENCY (Hz) Figure 33. Total Harmonic Distortion @ 1 kHz 1.620 1.625 1.630 –20 –30 –40 –50 –160 VDD = 5V TA = 25°C REFERENCE = 2.5V, ±0.1V p-p –60 10k 10797-149 THD (dBV) –60 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 1.615 –10 –40 0 1.
PAGE 16
AD5686/AD5684 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 8.
PAGE 17
Data Sheet AD5686/AD5684 Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec.
PAGE 18
AD5686/AD5684 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5686/AD5684 are quad, 16-/12-bit, serial input, voltage output DACs. The parts operate from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5686/AD5684 in a 24-bit word format via a 3-wire serial interface. The AD5686/AD5684 incorporate a power-on reset circuit to ensure that the DAC output powers up to a known output state.
PAGE 19
Data Sheet AD5686/AD5684 SERIAL INTERFACE Table 8. Command Bit Definitions The AD5686/AD5684 have a 3-wire serial interface (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI™, and MICROWIRE® interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The AD5686/AD5684 contain an SDO pin to allow the user to daisychain multiple devices together (see the Daisy-Chain Operation section) or for readback.
PAGE 20
AD5686/AD5684 Data Sheet STANDALONE OPERATION AD5686/ AD5684 68HC11* The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 24-bit input shift register on the falling edge of SCLK. After the last of 24 data bits is clocked in, SYNC should be brought high. The programmed function is then executed, that is, an LDAC-dependent change in DAC register contents and/or a change in the mode of operation.
PAGE 21
Data Sheet AD5686/AD5684 READBACK OPERATION Table 11. Modes of Operation Readback mode is invoked through a software executable readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again. Command 1001 is reserved for the readback function. This command, in association with selecting one of the address bits, DAC A to DAC D, selects the register to read.
PAGE 22
AD5686/AD5684 Data Sheet LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5686/AD5684 DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC register are controlled by the LDAC pin. Command 0101 is reserved for the software LDAC function. Address bits are ignored. Writing to the DAC using Command 0101 loads the 4-bit LDAC register (DB3 to DB0).
PAGE 23
Data Sheet AD5686/AD5684 HARDWARE RESET (RESET) RESET SELECT PIN (RSTSEL) RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the RESET select pin. It is necessary to keep RESET low for a minimum of 30 ns to complete the operation (see Figure 2). When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed.
PAGE 24
AD5686/AD5684 Data Sheet APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5686/AD5684 is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The devices require a 24-bit data-word with data valid on the rising edge of SYNC.
PAGE 25
Data Sheet AD5686/AD5684 CONTROLLER In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler® products from Analog Devices provide voltage isolation in excess of 2.5 kV.
PAGE 26
AD5686/AD5684 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 1.75 1.60 SQ 1.45 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN 08-16-2010-E 3.10 3.00 SQ 2.90 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 47.
PAGE 27
Data Sheet AD5686/AD5684 ORDERING GUIDE Model 1 AD5686ACPZ-RL7 AD5686BCPZ-RL7 AD5686ARUZ AD5686ARUZ-RL7 AD5686BRUZ AD5686BRUZ-RL7 AD5684BCPZ-RL7 AD5684ARUZ AD5684ARUZ-RL7 AD5684BRUZ AD5684BRUZ-RL7 EVAL-AD5686RSDZ EVAL-AD5684RSDZ 1 Resolution 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 12 Bits 12 Bits 12 Bits 12 Bits 12 Bits Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C