Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

4 × 12-Bit and 4 × 16-Bit Octal DAC with

On-Chip Reference in 14-Lead TSSOP

AD5678

Rev. C

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FEATURES

Low power octal DAC with

Four 16-bit DACs

Four 12-bit DACs

14-lead/16-lead TSSOP

On-chip 1.25 V/2.5 V, 5 ppm/°C reference

Power down to 400 nA @ 5 V, 200 nA @ 3 V

2.7 V to 5.5 V power supply

Guaranteed monotonic by design

Power-on reset to zero scale

3 power-down functions

Hardware

LDAC

and

LDAC

override function

CLR

function to programmable code

Rail-to-rail operation

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage current sources

Programmable attenuators

FUNCTIONAL BLOCK DIAGRAM

INTERFACE

LOGIC

INPUT

DIN

LDAC

GND

OUT

LDAC

REFIN

REFOUT

SYNC

SCLK

AD5678

CLR

RU-16 PACKAGE ONLY

1.25V/2.5V

REF

OUT

DAC

STRING

DAC A

BUFFER

INPUT

DAC

STRING

DAC B

BUFFER

INPUT

DAC

STRING

DAC C

BUFFER

INPUT

DAC

STRING

DAC D

BUFFER

INPUT

DAC

STRING

DAC E

BUFFER

INPUT

DAC

STRING

DAC F

BUFFER

INPUT

DAC

STRING

DAC G

BUFFER

INPUT

DAC

STRING

DAC H

BUFFER

POWER-DOWN

LOGIC

POWER-ON

RESET

05299-001

Figure 1.

GENERAL DESCRIPTION

The AD5678 is a low power, octal, buffered voltage-output

DAC with four 12-bit DACs and four 16-bit DACs in a single

package. All devices operate from a single 2.7 V to 5.5 V supply

and are guaranteed monotonic by design.

The AD5678 has an on-chip reference with an internal gain of 2.

The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full-

scale output of 2.5 V; the AD5678-2 has a 2.5 V 5 ppm/°C

reference, giving a full-scale output of 5 V. The on-board

reference is off at power-up, allowing the use of an external

reference. The internal reference is enabled via a software write.

The part incorporates a power-on reset circuit that ensures that

the DAC output powers up to 0 V and remains powered up at

this level until a valid write takes place. The part contains a

power-down feature that reduces the current consumption of

the device to 400 nA at 5 V and provides software-selectable

output loads while in power-down mode for any or all DAC

channels.

The outputs of all DACs can be updated simultaneously using

the

LDAC

function, with the added functionality of user-

selectable DAC channels to simultaneously update. There is

also an asynchronous

CLR

that clears all DACs to a software-

selectable code—0 V, midscale, or full scale.

The AD5678 utilizes a versatile 3-wire serial interface that

operates at clock rates of up to 50 MHz and is compatible with

standard SPI®, QSPI™, MICROWIRE™, and DSP interface

standards. The on-chip precision output amplifier enables rail-

to-rail output swing.

PRODUCT HIGHLIGHTS

1. Octal DAC (four 12-bit DACs and four 16-bit DACs).

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 14-lead/16-lead TSSOP.

4. Power-on reset to 0 V.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

Summary of content (28 pages)

PAGE 1
4 × 12-Bit and 4 × 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP AD5678 Low power octal DAC with Four 16-bit DACs Four 12-bit DACs 14-lead/16-lead TSSOP On-chip 1.25 V/2.5 V, 5 ppm/°C reference Power down to 400 nA @ 5 V, 200 nA @ 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale 3 power-down functions Hardware LDAC and LDAC override function CLR function to programmable code Rail-to-rail operation FUNCTIONAL BLOCK DIAGRAM VREFIN/VREFOUT VDD AD5678 1.
PAGE 2
AD5678 TABLE OF CONTENTS Features .............................................................................................. 1 D/A Section................................................................................. 20 Applications....................................................................................... 1 Resistor String............................................................................. 20 Functional Block Diagram ..........................................................
PAGE 3
AD5678 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 1.
PAGE 4
AD5678 Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5 V IDD (All Power-Down Modes) 5 VDD = 4.5 V to 5.5 V A Grade 1 Min Typ Max B Grade1 Min Typ Max Unit Conditions/Comments 4.5 4.5 5.5 V 5.5 1.3 2 1.8 2.6 1.3 2 1.8 2.6 mA mA All digital inputs at 0 or VDD, DAC active, excludes load current VIH = VDD and VIL = GND Internal reference off Internal reference on 0.4 1 0.
PAGE 5
AD5678 VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 6
AD5678 Parameter LOGIC INPUTS3 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 2.7 V to 3.6 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 2.7 V to 3.6 V A Grade 1 Min Typ Max B Grade1 Min Typ Max ±3 0.8 2 Unit Conditions/Comments ±3 0.8 μA V V pF All digital inputs VDD = 3 V VDD = 3 V 3.6 V 2 3 2.7 3 3.6 2.7 1.2 1.7 1.7 2.6 1.2 1.7 1.7 2.
PAGE 7
AD5678 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise Min Typ 6 1.5 4 0.1 −90 0.5 2.
PAGE 8
AD5678 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX VDD = 2.7 V to 5.
PAGE 9
AD5678 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND Digital Input Voltage to GND VREFIN/VREFOUT to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature (TJ MAX) TSSOP Package Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering SnPb Pb Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.
PAGE 10
AD5678 LDAC 1 16 SCLK SYNC 2 15 DIN AD5678 14 GND TOP VIEW (Not to Scale) 13 VOUTB 12 VOUTD 1 14 SCLK VDD 2 13 DIN VDD VOUTA 3 AD5678 12 GND VOUTA 4 VOUTC 4 11 VOUTB VOUTC 5 VOUTE 5 TOP VIEW (Not to Scale) 10 VOUTD VOUTE 6 11 VOUTF VOUTG 6 9 VOUTF VOUTG 7 10 VOUTH VREFIN/VREFOUT 7 8 VOUTH VREFIN/VREFOUT 8 9 05299-003 SYNC Figure 3. 14-Lead TSSOP (RU-14) 3 CLR 05299-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4.
PAGE 11
AD5678 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 10 VDD = VREF = 5V TA = 25°C 8 0.6 DNL ERROR (LSB) 6 2 0 –2 –4 0.4 0.2 0 –0.2 –0.4 –0.8 05299-011 60000 65000 65000 55000 60000 50000 45000 40000 35000 30000 25000 20000 15000 –1.0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 10000 0 0 –8 05299-014 –0.6 –6 5000 INL ERROR (LSB) 4 –10 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.8 CODE Figure 8. DNL 16-Bit DAC, 2.5 V Internal Reference Figure 5. INL—16-Bit DAC 10 1.0 0.
PAGE 12
AD5678 1.0 VDD = VREF = 5V 0.8 TA = 25°C 0.20 0.10 DNL ERROR (LSB) 0.2 0 –0.2 –0.4 –0.6 0.05 0 –0.05 05299-045 –0.10 0 500 1000 1500 2000 2500 CODE 3000 3500 –0.15 4000 –0.20 Figure 11. INL—12-Bit DAC 0.20 0.6 0.05 INL ERROR (LSB) 1500 2000 2500 CODE 3000 3500 4000 0 –0.05 0.4 0.2 0 –0.2 –0.4 –0.6 05299-046 –0.15 0 500 1000 1500 2000 2500 CODE 3000 3500 05299-049 DNL ERROR (LSB) 1000 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.8 –0.10 –0.8 –1.0 4000 0 Figure 12.
PAGE 13
AD5678 1.0 0 –0.02 TA = 25°C VDD = 5V 0.5 –0.04 GAIN ERROR 0 ERROR (mV) ERROR (% FSR) –0.06 –0.08 –0.10 –0.12 –0.14 ZERO-SCALE ERROR –0.5 –1.0 –1.5 FULL-SCALE ERROR –0.20 –40 –2.0 05299-017 –0.18 –20 0 20 40 60 TEMPERATURE (°C) 80 –2.5 2.7 100 Figure 17. Gain Error and Full-Scale Error vs. Temperature 3.2 3.7 4.2 VDD (V) 4.7 5.2 Figure 20. Zero-Scale Error and Offset Error vs. Supply Voltage 20 1.5 1.0 OFFSET ERROR 05299-020 –0.16 18 VDD = 3.6V VDD = 5.
PAGE 14
AD5678 0.50 2.0 DAC LOADED WITH FULL-SCALE SOURCING CURRENT 0.40 DAC LOADED WITH ZERO-SCALE SINKING CURRENT VDD = VREF = 5V 1.6 0.30 1.4 0.20 0.10 IDD (mA) VDD = 3V VREFOUT = 1.25V 0 –0.10 1.2 VDD = VREF = 3V 1.0 0.8 0.6 –0.20 –0.40 –0.50 –10 –8 –6 –4 –2 0 2 CURRENT (mA) 4 6 8 05299-026 0.4 VDD = 5V VREFOUT = 2.5V –0.30 05299-023 ERROR VOLTAGE (V) TA = 25°C 1.8 0.2 0 512 10 Figure 23. Headroom at Rails vs. Source and Sink 10512 20512 1.6 5.00 1.4 1.
PAGE 15
AD5678 8 TA = 25°C VDD = VREF = 5V TA = 25°C 7 6 5 IDD (mA) VDD 4 1 VDD = 5V 3 2 VDD = 3V 0 1 2 3 VLOGIC (V) 4 5 05299-032 0 2 05299-029 1 VOUT 6 CH1 2.0V CH2 1.0V M100μs 125MS/s A CH1 1.28V 8.0ns/pt Figure 32. Power-On Reset to Midscale Figure 29. Supply Current vs. Logic Input Voltage SYNC 1 SLCK 3 VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND VOUT VOUT = 909mV/DIV 1 VDD = 5V 05299-033 05299-030 2 CH1 5.
PAGE 16
AD5678 2.5000 VDD = 5V VREFOUT = 2.5V TA = 25°C DAC LOADED WITH MIDSCALE 2.4995 2.4990 2.4980 10μV/DIV VOUT (V) 2.4985 2.4975 2.4970 1 2.4965 2.4950 0 64 128 192 256 320 SAMPLE 384 05299-035 VDD = 5V VREFOUT = 2.5V TA = 25°C 4ns/SAMPLE NUMBER 2.4955 05299-038 2.4960 512 448 5s/DIV Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference Figure 35. Analog Crosstalk 2.4900 VDD = 3V VREFOUT = 1.25V TA = 25°C DAC LOADED WITH MIDSCALE 2.4895 2.4890 5μV/DIV 2.4880 2.
PAGE 17
AD5678 –20 VDD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ± 0.3V p-p –30 –40 CLR 3 VOUT F (dB) –50 –60 –70 –80 VOUT B –100 2k 4k 6k FREQUENCY (Hz) 8k 05299-043 4 05299-041 –90 2 10k CH3 5.0V Figure 41. Total Harmonic Distortion CH2 1.0V CH4 1.0V M200ns A CH3 1.10V Figure 43. Hardware CLR 16 5 VREF = VDD TA = 25°C VDD = 5V TA = 25°C 0 14 –5 VDD = 3V (dB) –10 10 VDD = 5V 8 –15 –20 –25 –30 6 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9 10 Figure 42.
PAGE 18
AD5678 TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Figure 5, Figure 7, and Figure 9 show plots of typical INL vs. code. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VDD − 1 LSB.
PAGE 19
AD5678 Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output.
PAGE 20
AD5678 THEORY OF OPERATION D/A SECTION R The AD5678 DAC is fabricated on a CMOS process. The architecture consists of a string of DACs followed by an output buffer amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 45 shows a block diagram of the DAC architecture. R TO OUTPUT AMPLIFIER R VDD REF (+) RESISTOR STRING R OUTPUT AMPLIFIER (GAIN = +2) GND R 05299-006 REF (–) VOUT 05299-005 DAC REGISTER Figure 45.
PAGE 21
AD5678 Table 7. Command Definitions OUTPUT AMPLIFIER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The amplifier is capable of driving a load of 2 kΩ in parallel with 1,000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 24 and Figure 25. The slew rate is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs.
PAGE 22
AD5678 INPUT SHIFT REGISTER SYNC INTERRUPT The input shift register is 32 bits wide. The first four bits are don’t cares. The next four bits are the command bits, C3 to C0 (see Table 7), followed by the 4-bit DAC address bits, A3 to A0 (see Table 8), and finally the 16-/12-bit data-word. The dataword comprises the 16-/12-bit input code followed by four or eight don’t care bits for the AD5678 DAC A, B, G, H and AD5678 DAC C, D, E, F, respectively (See Figure 47 and Figure 48).
PAGE 23
AD5678 INTERNAL REFERENCE REGISTER The on-board reference is off at power-up by default. This allows the use of an external reference if the application requires it. The on-board reference can be turned on/off by a userprogrammable internal REF register by setting Bit DB0 high or low (see Table 9). Command 1000 is reserved for this internal REF set-up command (see Table 7). Table 11 shows the state of the bits in the input shift register corresponds to the mode of operation of the device.
PAGE 24
AD5678 Table 9. Internal Reference Register Internal REF Register (DB0) 0 1 Action Reference off (default) Reference on Table 10. 32-Bit Input Shift Register Contents for Reference Set-Up Function MSB DB31 to DB28 X Don’t cares DB27 DB26 DB25 DB24 1 0 0 0 Command bits (C3 to C0) DB23 X DB22 DB21 DB20 X X X Address bits (A3 to A0) DB19 to DB1 X Don’t cares LSB DB0 1/0 Internal REF register Table 11.
PAGE 25
AD5678 LDAC FUNCTION POWER SUPPLY BYPASSING AND GROUNDING The outputs of all DACs can be updated simultaneously using the hardware LDAC pin. When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5678 should have separate analog and digital sections. If the AD5678 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only.
PAGE 26
AD5678 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 0.30 0.19 0.75 0.60 0.45 8° 0° 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 51. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 0.
PAGE 27
AD5678 NOTES Rev.