Datasheet

Data Sheet AD5629R/AD5669R
Rev. B | Page 7 of 32
I
2
C TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, f
SCL
= 400 kHz, unless otherwise noted.
Table 4.
Parameter Conditions Min Max Unit Description
f
SCL
1
Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
t
1
Standard mode 4 μs t
HIGH
, SCL high time
Fast mode 0.6 μs
t
2
Standard mode 4.7 μs t
LOW
, SCL low time
Fast mode
1.3
μs
t
3
Standard mode 250 ns t
SU;DAT
, data setup time
Fast mode 100 ns
t
4
Standard mode 0 3.45 μs t
HD;DAT
, data hold time
Fast mode 0 0.9 μs
t
5
Standard mode 4.7 μs t
SU;STA
, setup time for a repeated start condition
Fast mode
0.6
μs
t
6
Standard mode 4 μs t
HD;STA
, hold time (repeated) start condition
Fast mode 0.6 μs
t
7
Standard mode 4.7 μs t
BUF
, bus-free time between a stop and a start condition
Fast mode 1.3 μs
t
8
Standard mode 4 μs t
SU;STO
, setup time for a stop condition
Fast mode 0.6 μs
t
9
Standard mode 1000 ns t
RDA
, rise time of SDA signal
Fast mode 300 ns
t
10
Standard mode 300 ns t
FDA
, fall time of SDA signal
Fast mode 300 ns
t
11
Standard mode
1000
ns
t
RCL
, rise time of SCL signal
Fast mode 300 ns
t
11A
Standard mode 1000 ns
t
RCL1
, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
Fast mode 300 ns
t
12
Standard mode
300
ns
t
FCL
, fall time of SCL signal
Fast mode 300 ns
t
13
Standard mode 10 ns
LDAC pulse width low
Fast mode 10 ns
t
14
Standard mode 300 ns
Falling edge of ninth SCL clock pulse of last byte of a valid write to
the LDAC falling edge
Fast mode
300
ns
t
15
Standard mode 20 ns
CLR pulse width low
Fast mode 20 ns
t
SP
2
Fast mode 0 50 ns Pulse width of spike suppressed
1
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
2
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.