Datasheet

AD5629R/AD5669R Data Sheet
Rev. B | Page 24 of 32
INTERNAL REFERENCE REGISTER
The internal reference is available on all versions. The on-board
reference is off at power-up by default. The on-board reference
can be turned off or on by a user-programmable internal REF
register by setting Bit DB0 high or low (see Tabl e 10). DB1
selects the internal reference value. Command 1000 is reserved
for setting the internal REF register (see Table 8). Tabl e 11
shows how the state of the bits in the input shift register
corresponds to the mode of operation of the device.
POWER-ON RESET
The AD5629R/AD5669R contain a power-on reset circuit that
controls the output voltage during power-up. The AD5629R/
AD5669R DAC output powers up to 0 V and the AD5669R-3
DAC output powers up to midscale. The output remains
powered up at this level until a valid write sequence is made
to the DAC. This is useful in applications where it is important
to know the state of the output of the DAC while it is in the
process of powering up. There is also a software executable
reset function that resets the DAC to the power-on reset code.
Command 0111 is reserved for this reset function (see Table 8
).
Any events on
A
LDAC
E
A
or A
CLR
E
A
during power-on reset are
ignored.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND
DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
08819-050
Figure 53. AD5669R Input Register Contents
DB23
DB22
DB21 DB20
DB19 DB18 DB17
DB16 DB15 DB14
DB13 DB12
DB11
DB10 DB9 DB8
DB7 DB6
DB5 DB4
DB3 DB2
DB1 DB0
C3 C2 C1
C0 A3
A2
A1 A0 D11
D10 D9 D8
D7 D6
D5
D4 D3 D2
D1 D0 X
X
X X
COMMAND
DAC ADDRESS DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE DATA LOW BYTE
08819-052
Figure 54. AD5629R Input Register Contents