Datasheet
Data Sheet AD5628/AD5648/AD5668
Rev. G | Page 9 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
05302-003
1
2
3
4
5
6
7
AD5628/
AD5648/
V
DD
V
OUT
A
V
OUT
C
V
REFIN
/V
REFOUT
V
OUT
G
V
OUT
E
14
13
12
11
10
9
8
DIN
GND
V
OUT
B
V
OUT
H
V
OUT
F
V
OUT
D
SCLK
TOP VIEW
(Not to Scale)
SYNC
Figure 3. 14-Lead TSSOP (RU-14)
05302-004
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
V
DD
V
OUT
A
V
OUT
G
V
OUT
E
V
OUT
C
LDAC
DIN
GND
V
OUT
B
V
OUT
H
V
REFIN
/V
REFOUT
CLR
V
OUT
F
V
OUT
D
SCLK
AD5628/
AD5648/
AD5668
TOP VIEW
(Not to Scale)
Figure 4. 16-Lead TSSOP (RU-16)
05302-005
12
11
10
1
3
4
GND
V
OUT
B
V
OUT
D
9
V
OUT
F
V
DD
V
OUT
C
2
V
OUT
A
V
OUT
E
6
V
REFIN
/V
REFOUT
5
V
OUT
G
7
CLR
8
V
OUT
H
16 SYNC
15
LDAC
14
SCLK
13
D
IN
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD MUST BE TIED TO GND.
AD5628/AD5668
Figure 5. 16-Lead LFCSP(CP-16-17)
Table 6. Pin Function Descriptions
Pin No.
14-Lead
TSSOP
16-Lead
TSSOP
16-Lead
LFCSP Mnemonic Description
N/A
1
15
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively, this
pin can be tied permanently low.
1 2 16
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC
goes low, it powers on the SCLK and DIN buffers and enables the input shift
register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC
is taken
high before the 32
nd
falling edge, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the device.
2 3 1 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply
should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
3 4 2 V
OUT
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
11 13 11 V
OUT
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4 5 3 V
OUT
C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
10 12 10 V
OUT
D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7 8 6
V
REFIN
/
V
REFOUT
The AD5628/AD5648/AD5668 have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When using
an external reference, this is the reference input pin. The default for this pin is as a
reference input.
N/A 9 7
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC
pulses are ignored. When CLR is activated, the input register and the DAC register
are updated with the data contained in the CLR code register—zero, midscale, or full
scale. Default setting clears the output to 0 V.
5 6 4 V
OUT
E Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
9 11 9 V
OUT
F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
6 7 5 V
OUT
G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
8 10 8 V
OUT
H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
12 14 12 GND Ground Reference Point for All Circuitry on the Part.
13 15 13 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register
on the falling edge of the serial clock input.
14 16 14 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. Data can be transferred at rates of up to 50 MHz.
EPAD EPAD It is recommended that the exposed paddle be soldered to the ground plane.