Datasheet

AD5628/AD5648/AD5668 Data Sheet
Rev. G | Page 26 of 32
LDAC
FUNCTION
The outputs of all DACs can be updated simultaneously using
the hardware
LDAC
pin.
Synchronous
LDAC
: After new data is read, the DAC registers
are updated on the falling edge of the 32
nd
SCLK pulse.
LDAC
can be permanently low or pulsed as in
Figure 2.
Asynchronous
LDAC
: The outputs are not updated at the same
time that the input registers are written to. When
LDAC
goes
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software
LDAC
function by writing to Input
Register n and updating all DAC registers. Command 0011 is
reserved for this software
LDAC
function.
An
LDAC
register gives the user extra flexibility and control
over the hardware
LDAC
pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware
LDAC
pin is executed. Setting the
LDAC
bit
register to 0 for a DAC channel means that this channel’s update
is controlled by the
LDAC
pin. If this bit is set to 1, this channel
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the
LDAC
pin. It
effectively sees the
LDAC
pin as being tied low. (See Table 16
for the
LDAC
register mode of operation.) This flexibility is
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using command 0110 loads the 8-bit
LDAC
register (DB7 to DB0). The default for each channel is 0, that is,
the
LDAC
pin works normally. Setting the bits to 1 means the
DAC channel is updated regardless of the state of the
LDAC
pin. See Table 17 for the contents of the input shift register
during the load
LDAC
register mode of operation.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5628/AD5648/
AD5668 should have separate analog and digital sections. If the
AD5628/AD5648/AD5668 are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5628/AD5648/AD5668.
The power supply to the AD5628/AD5648/AD5668 should be
bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should physically be as close as possible to the device, with the
0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the
0.1 µF capacitor has low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
Table 16.
LDAC
Register
Load DAC Register
LDAC
Bits (DB7 to DB0)
LDAC
Pin
LDAC
Operation
0 1/0 Determined by
LDAC
pin.
1 X—don’t care DAC channels update, overriding the
LDAC
pin. DAC channels see
LDAC
as 0.
Table 17. 32-Bit Input Shift Register Contents for
LDAC
Register Function
MSB LSB
DB31
to
DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20
DB19
to
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
0
1
1
0
X
X
X
X
X
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Don’t
cares
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Setting
LDAC
bit to 1 overrides
LDAC
pin