Datasheet

AD5627R/AD5647R/AD5667R, AD5627/AD5667
Rev. 0 | Page 25 of 32
Synchronous
LDAC
The DAC registers are updated after new data is read in.
LDAC
can be permanently low or pulsed.
Asynchronous
LDAC
The outputs are not updated at the same time that the input
registers are written to. When
LDAC
goes low, the DAC
registers are updated with the contents of the input register.
The
LDAC
register gives the user full flexibility and control over
the hardware
LDAC
pin. This register allows the user to select
which combination of channels to simultaneously update when
the hardware
LDAC
pin is executed. Setting the
LDAC
bit
register to 0 for a DAC channel means that the update of this
channel is controlled by the
LDAC
pin. If this bit is set to 1, this
channel synchronously updates, that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC
pin. It effectively sees the
LDAC
pin as being pulled low.
See
Table 10 for the
LDAC
register mode of operation. This
flexibility is useful in applications when the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Writing to the DAC using Command 110 loads the 2-bit
LDAC
register [DB1:DB0]. The default for each channel is 0, that is,
the
LDAC
pin works normally. Setting the bits to 1 means the
DAC register is updated, regardless of the state of the
LDAC
pin. See
Figure 63 for contents of the input shift register during
the
LDAC
register setup command.
Table 10.
LDAC
Register Mode of Operation:
Load DAC Register
LDAC
Bits
(DB1 to DB0)
LDAC
Pin
LDAC
Operation
0 1/0
Determined by
LDAC pin.
1 x = don’t care
The DAC registers are updated
after new data is read in.
POWER-DOWN MODES
Command 100 is reserved for the power-up/down function.
The power-up/down modes are programmed by setting Bit
DB5 and Bit DB4. This defines the output state of the DAC
amplifier, as shown in
Table 11. Bit DB1and Bit DB0 determine
to which DAC or DACs the power-up/down command is
applied. Setting one of these bits to 1 applies the power-up/down
state defined by DB5 and DB4 to the corresponding DAC. If a
bit is 0, the state of the DAC is unchanged.
Figure 65 shows the
contents of the input shift register for the power up/down
command.
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 400 µA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 k or 100 k resistor, or left
open-circuited (three-state) as shown in
Figure 62.
Table 11. Modes of Operation for the AD56x7R/AD56x7
DB5 DB4 Operating Mode
0 0 Normal operation
Power-down modes
0 1 1 kΩ pull-down to GND
1 0 100 kΩ pull-down to GND
1 1 Three-state, high impedance
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
06342-038
Figure 62. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 µs for V
DD
= 5 V.
R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
1 1 0 A2 A1 A0 X X X X X X X X X X X X X X DACB DACA
COMMAND
DAC ADDRESS
(DON’T CARE)
DON’T CARE DON’T CARE
DAC SELECT
(0 = LDAC PIN ENABLED)
06342-111
Figure 63.
LDAC
Setup Command