Datasheet

AD5666
Rev. D | Page 11 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05298-005
1
2
3
4
5
6
7
AD5666
V
DD
V
OUT
A
V
REFIN
/V
REFOUT
POR
V
OUT
C
14
13
12
11
10
9
8
DIN
GND
V
OUT
B
SDO
V
OUT
D
SCLK
TOP VIEW
(Not to Scale)
LDAC
CLR
SYNC
Figure 5. 14-Lead TSSOP (RU-14)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the next 32 clocks. If SYNC
is taken high before the 32
nd
falling edge, the rising
edge of SYNC acts as an interrupt and the write sequence is ignored by the device.
3 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 V
OUT
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5 V
OUT
C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6 POR
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to V
DD
powers up
the part to midscale.
7 V
REFIN
/V
REFOUT
The AD5666 has a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
8 SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading
back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge
of SCLK and is valid on the falling edge of the clock.
9
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR
is activated, the input register and the DAC register are updated with the data
contained in the CLR
code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
10 V
OUT
D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
11 V
OUT
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
12 GND Ground Reference Point for All Circuitry on the Part.
13 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
14 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.