Datasheet

AD5666
Rev. D | Page 8 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 3 and
Figure 5. V
DD
= 2.7 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Limit at T
MIN
, T
MAX
Parameter V
DD
= 2.7 V to 5.5 V Unit Conditions/Comments
t
1
1
20 ns min SCLK cycle time
t
2
8 ns min SCLK high time
t
3
8 ns min SCLK low time
t
4
13 ns min
SYNC
to SCLK falling edge set-up time
t
5
4 ns min Data set-up time
t
6
4 ns min Data hold time
t
7
0 ns min
SCLK falling edge to SYNC
rising edge
t
8
15 ns min
Minimum SYNC
high time
t
9
13 ns min
SYNC
rising edge to SCLK fall ignore
t
10
0 ns min
SCLK falling edge to SYNC
fall ignore
t
11
10 ns min
LDAC
pulse width low
t
12
15 ns min
SCLK falling edge to LDAC
rising edge
t
13
5 ns min
CLR
pulse width low
t
14
0 ns min
SCLK falling edge to LDAC
falling edge
t
15
300 ns typ
CLR
pulse activation time
t
16
2, 3
22 ns max SCLK rising edge to SDO valid
t
17
3
5 ns min
SCLK falling edge to SYNC
rising edge
t
18
3
8 ns min
SYNC
rising edge to SCLK rising edge
t
19
3
0 ns min
SYNC
rising edge to LDAC falling edge
1
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Measured with the load circuit of Figure 16. t
16
determines the maximum SCLK frequency in daisy-chain mode.
3
Daisy-chain mode only.
2mA I
OL
2mA I
OH
V
OH
(MIN)
TO OUTPUT
PIN
C
L
50pF
0
5298-002
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications