Datasheet

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. C | Page 9 of 36
Parameter Test Conditions
2
Min Max Unit Description
t
12
Standard mode 300 ns t
FCL
, fall time of SCL signal
Fast mode 300 ns
High speed mode, C
B
= 100 pF 10 40 ns
High speed mode, C
B
= 400 pF 20 80 ns
t
13
Standard mode
10
ns
LDAC
pulse width low
Fast mode 10 ns
High speed mode 10 ns
t
14
Standard mode 300 ns Falling edge of ninth SCL clock pulse of last byte
of a valid write to
LDAC
falling edge
Fast mode 300 ns
High speed mode 30 ns
t
15
Standard mode 20 ns
CLR
pulse width low
Fast mode 20 ns
High speed mode 20 ns
t
SP
4
Fast mode 0 50 ns Pulse width of spike suppressed
High speed mode
0
10
ns
1
See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.
2
C
B
refers to the capacitance on the bus line.
3
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
4
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
Figure 3. 2-Wire Serial Interface Timing Diagram
SCL
SDA
P S S
P
t
8
t
6
t
5
t
3
t
10
t
9
t
4
t
6
t
1
t
2
t
11
t
12
t
14
CLR
t
13
t
15
LDAC*
t
7
*ASYNCHRONOUS LDAC UPDATE MODE.
06341-003