Datasheet

AD5663
Rev. 0 | Page 18 of 24
MICROPROCESSOR INTERFACING
AD5663 to Blackfin® ADSP BF53x Interface
Figure 32 shows a serial interface between the AD5663 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor
family incorporates two dual-channel synchronous serial ports,
SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5663, the
setup for the interface is as follows:
• DT0PRI drives the DIN pin of the AD5663.
• TSCLK0 drives the SCLK of the part.
• The
SYNC
pin is driven from TFS0.
AD5663
1
ADSP-BF53x
1
SYNC
TFS0
DINDTOPRI
SCLKTSCLK0
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05855-037
Figure 32. AD5663 to Blackfin ADSP-BF53x Interface
AD5663 to 68HC11/68L11 Interface
Figure 33 shows a serial interface between the AD5663 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5663, and the MOSI output drives
the serial data line of the DAC.
The
SYNC
signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
• The 68HC11/68L11 is configured with its CPOL bit as 0.
• The 68HC11/68L11 is configured with its CPHA bit as 1.
When data is being transmitted to the DAC, the
SYNC
line is
taken low (PC7). When the 68HC11/68L11 is configured as
previously described, data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 10-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5663, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
AD5663
1
68HC11/68L11
1
SYNC
PC7
SCLKSCK
DINMOSI
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05855-038
Figure 33. AD5663 to 68HC11/68L11 Interface
AD5663 to 80C51/80L51 Interface
Figure 34 shows a serial interface between the AD5663 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows:
• TxD of the 80C51/80L51 drives SCLK of the AD5663.
• RxD drives the serial data line of the part.
The
SYNC
signal is again derived from a bit-programmable pin
on the port. In this case, Port Line P3.3 is used. When data is to be
transmitted to the AD5663, P3.3 is taken low. The 80C51/80L51
transmits data in 10-bit bytes only; thus only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 outputs the serial data in a format that has the LSB first.
The AD5663 must receive data with the MSB first. The 80C51/
80L51 transmit routine should take this into account.
AD5663
1
80C51/80L51
1
SYNC
P3.3
SCLKTxD
DINRxD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05855-039
Figure 34. AD5663 to 80C51/80L51 Interface
AD5663 to MICROWIRE Interface
Figure 35 shows an interface between the AD5663 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5663
on the rising edge of the SK.
AD5663
1
MICROWIRE
1
SYNC
CS
SCLKSK
DINSO
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05855-040
Figure 35. AD5663 to MICROWIRE Interface