Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) MSOP 10

AD5663

Rev. 0 | Page 17 of 24

Synchronous

LDAC

: The DAC registers are updated after new

data is read in on the falling edge of the 24th SCLK pulse.

LDAC

can be permanently low or pulsed, as shown in Figure 2.

Asynchronous

LDAC

: The outputs are not updated at the same

time that the input registers are written to. When

LDAC

goes

low, the DAC registers are updated with the contents of the

input register.

The

LDAC

over the hardware

LDAC

pin. This register allows the user to

select which combination of channels to simultaneously update

when the hardware

LDAC

pin is executed. Setting the

LDAC

bit

channel is controlled by the

LDAC

pin. If this bit is set to 1, this

channel synchronously updates; that is, the DAC register is

updated after new data is read in, regardless of the state of the

LDAC

pin. It effectively sees the

LDAC

pin as being pulled low.

See

Table 13 for the

LDAC

This flexibility is useful in applications where the user wants to

simultaneously update select channels while the rest of the

channels are synchronously updating

Writing to the DAC using Command 110 loads the 2-bit

LDAC

the

LDAC

pin works normally. Setting the bits to 1 means the

DAC register is updated regardless of the state of the

LDAC

pin.

See

Table 14 for contents of the input shift register during the

LDAC

Table 13.

LDAC

Bits

(DB1 to DB0)

LDAC

Operation

0 1/0

Determined by

LDAC pin

1 x = don’t care

The DAC registers are updated

after new data is read in on the

falling edge of the 24th SCLK

pulse

Table 14. 24-Bit Input Shift Register Contents for

LDAC

MSB

LSB

DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0

x 1 1 0 x x x x DAC B DAC A

Don’t care Command bits (C2 to C0) Address bits (A3 to A0);

Don’t care

Set DAC to 0 or 1 for required mode of

operation