Datasheet

AD5663
Rev. 0 | Page 14 of 24
THEORY OF OPERATION
D/A SECTION
The AD5663 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier.
Figure 27 shows a block diagram of the DAC
architecture.
DAC
REGISTER
RESISTOR
STRING
REF (+)
V
DD
GND
REF (–)
V
OUT
OUTPUT
AMPLIFIER
(GAIN = +2)
05855-032
Figure 27. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
⎟
⎠
⎞
⎜
⎝
⎛
×=
65,536
D
VV
REF
OUT
where D is the decimal equivalent of the binary code that is
loaded to the DAC register. It can range from 0 to 65,535.
RESISTOR STRING
The resistor string section is shown in Figure 28. It is a string of
resistors, each of Value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
0
5855-033
Figure 28. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
DD
. It can drive
a load of 2 k in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be
seen in
Figure 14. The slew rate is 1.8 V/µs with a 1/4 to 3/4
full-scale settling time of 10 µs.
SERIAL INTERFACE
The AD5663 has a 3-wire serial interface (
SYNC
, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as with most DSPs. See
Figure 2 for
a timing diagram of a typical write sequence.
The write sequence begins by bringing the
SYNC
line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5663 compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed; that is, there is a
change in DAC register contents and/or a change in the mode
of operation. At this stage, the
SYNC
line can be kept low or be
brought high. In either case, it must be brought high for a mini-
mum of 15 ns before the next write sequence so that a falling edge
of
SYNC
can initiate the next write sequence. Because the
SYNC
buffer draws more current when V
IN
= 2.0 V than it does when
V
IN
= 0.10 V,
SYNC
should be idled low between write sequences
for even lower power operation. As mentioned previously,
however, it must be brought high again just before the next
write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 29). The first
two bits are don’t cares. The next three are the Command Bit C2
to Command Bit C0 (see
Table 7), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see
Table 8), and, finally, the
16-bit data-word. These are transferred to the DAC register on
the 24th falling edge of SCLK.
Table 7. Command Definition
C2 C1 C0 Command
0 0 0 Write to input register n
0 0 1 Update DAC register n
0 1 0
Write to input register n, update all
(software
LDAC)
0 1 1 Write to and update DAC channel n
1 0 0 Power down DAC (power up)
1 0 1 Reset
1 1 0
LDAC register setup
1 1 1 Reserved