Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) MSOP 10

2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output,

Dual 16-Bit nanoDAC

AD5663

Rev. 0

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FEATURES

Low power, dual 16-bit nanoDAC

Relative accuracy: ±12 LSBs maximum

Guaranteed monotonic by design

10-lead MSOP and 3 mm × 3 mm LFCSP_WD

2.7 V to 5.5 V power supply

Per channel power-down

Power-on reset to zero scale or midscale

Hardware

LDAC

and

CLR

functions

Serial interface; up to 50 MHz

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

FUNCTIONAL BLOCK DIAGRAM

INTERFACE

LOGIC

SCLK

SYNC

DIN

CLR

INPUT

DAC

GND

POWER-ON

RESET

STRING

DAC A

STRING

DAC B

BUFFER

REF

POWER-DOWN

LOGIC

OUT

AD5663

LDAC

05855-001

Figure 1.

Table 1. Related Devices

Part No. Description

AD5623R/AD5643R/AD5663R

2.7 V to 5.5 V, dual 12-/14-/16-bit

DACs with internal reference

GENERAL DESCRIPTION

The AD5663, a member of the nanoDAC family, is a low power,

dual, 16-bit buffered voltage-out DAC that operates from a single

2.7 V to 5.5 V supply and is guaranteed monotonic by design.

The AD5663 requires an external reference voltage to set the

output range of the DAC. The part incorporates a power-on

reset circuit that ensures the DAC output powers up to 0 V or

midscale (AD5663-1) and remains there until a valid write takes

place. The part contains a power-down feature that reduces the

current consumption of the device to 480 nA at 5 V and provides

software-selectable output loads while in power-down mode.

The low power consumption of this part in normal operation

makes it ideally suited to portable, battery-operated equipment.

The power consumption is 1.25 mW at 5 V, going down to

2.4 µW in power-down mode.

The on-chip precision output amplifier of the AD5663 allows

rail-to-rail output swing to be achieved.

The AD5663 uses a versatile, 3-wire serial interface that

operates at clock rates up to 50 MHz and is compatible with

standard SPI®, QSPI™, MICROWIRE™, and DSP interface

standards.

PRODUCT HIGHLIGHTS

1. Dual 16-bit DAC; relative accuracy of ±12 LSBs maximum.

2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm

LFCSP_WD packages.

3. Low power; typically consumes 0.6 mW at 3 V and

1.25 mW at 5 V.

4. 7 µs maximum settling time.

Summary of content (24 pages)

PAGE 1
2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output, Dual 16-Bit nanoDAC® AD5663 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD SCLK SYNC INPUT REGISTER DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INTERFACE LOGIC DIN AD5663 POWER-ON RESET GENERAL DESCRIPTION The AD5663, a member of the nanoDAC family, is a low power, dual, 16-bit buffered voltage-out DAC that operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design.
PAGE 2
AD5663 TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier........................................................................ 14 Applications....................................................................................... 1 Serial Interface ............................................................................ 14 Functional Block Diagram .............................................................
PAGE 3
AD5663 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD5663 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise 1 2 Min Typ 4 1.8 10 0.1 −90 0.
PAGE 5
AD5663 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 4. Limit at TMIN, TMAX VDD = 2.7 V to 5.
PAGE 6
AD5663 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VOUT to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation LFCSP_WD Package (4-Layer Board) θJA Thermal Impedance MSOP Package (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.
PAGE 7
AD5663 PIN CONFIGURATION AND FUNCTION DESCRIPTION VOUTB 2 GND 3 LDAC 4 CLR 5 10 VREF AD5663 9 VDD TOP VIEW (Not to Scale) 8 DIN 7 SCLK 6 SYNC 05855-003 VOUTA 1 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic VOUTA VOUTB GND LDAC 5 CLR 6 SYNC 7 SCLK 8 DIN 9 VDD 10 VREF Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B.
PAGE 8
AD5663 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 6 VDD = 5V TA = 25°C 4 4 ERROR (LSB) 2 0 –2 2 MAX DNL 0 MIN DNL –2 –4 –4 –6 –6 MIN INL 05855-004 –8 –8 0 –10 0.75 1.25 1.75 2.25 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 2.75 3.25 VREF (V) 3.75 4.25 05855-007 INL ERROR (LSB) 6 –10 MAX INL 8 VDD = VREF = 5V TA = 25°C 8 4.75 Figure 7. INL and DNL Error vs. VREF Figure 4. INL 8 1.0 VDD = VREF = 5V TA = 25°C MAX INL 6 TA = 25°C 0.6 4 0.
PAGE 9
AD5663 1.5 VDD = 5.5V TA = 25°C 1.0 8 ZERO-SCALE ERROR NUMBER OF UNITS ERROR (mV) 0.5 0 –0.5 –1.0 6 4 2 –1.5 –2.5 –40 05855-010 –2.0 –20 0 20 40 60 TEMPERATURE (°C) 80 0 0.230 100 Figure 10. Zero-Scale and Offset Error vs. Temperature 0.240 0.245 IDD (mA) 0.250 0.255 Figure 13. IDD Histogram with VDD = 5.5 V 0.20 1.0 0.5 DAC LOADED WITH ZERO SCALE – SINKING CURRENT VDD = VREF = 5V, 3V TA = 25°C 0.15 ERROR VOLTAGE (V) 0.10 GAIN ERROR ERROR (% FSR) 0.
PAGE 10
AD5663 VOUT = 909mV/DIV 05855-019 1 VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 05855-058 VOUT (V) VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 0 50 100 150 TIME BASE = 4µs/DIV 200 250 300 350 SAMPLE NUMBER 400 450 512 Figure 19.
PAGE 11
AD5663 16 5 VREF = VDD TA = 25°C VDD = 5V TA = 25°C 0 14 –5 VDD = 3V –10 –15 (dB) TIME (µs) 12 10 –20 VDD = 5V 8 –25 –30 6 0 1 2 3 4 5 6 7 CAPACITANCE (nF) 8 9 05855-029 05855-026 4 –35 –40 10k 10 100k 1M FREQUENCY (Hz) Figure 22. Settling Time vs. Capacitive Load 10M Figure 25. Multiplying Bandwidth VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE CLR 3 VOUT A 1 VOUT B 05855-027 2 CH3 5.0V Figure 23. 0.
PAGE 12
AD5663 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 4.
PAGE 13
AD5663 Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth.
PAGE 14
AD5663 THEORY OF OPERATION D/A SECTION OUTPUT AMPLIFIER The AD5663 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a block diagram of the DAC architecture. The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 kΩ in parallel with 1000 pF to GND.
PAGE 15
AD5663 Table 8. Address Command A2 0 0 0 0 1 A1 0 0 1 1 1 SOFTWARE RESET A0 0 1 0 1 1 ADDRESS (n) DAC A DAC B Reserved Reserved All DACs The AD5663 contains a software reset function. Command 101 is reserved for the software reset function (see Table 7). The software reset command contains two reset modes that are software-programmable by setting Bit DB0 in the control register. Table 9 shows how the state of the bit corresponds to the mode of operation of the device.
PAGE 16
AD5663 POWER-DOWN MODES The AD5663 contains four separate modes of operation. Command 100 is reserved for the power-down function (see Table 7). These modes are software-programmable by setting Bit DB5 and Bit DB4 in the control register. Table 11 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC B and DAC A) can be powered down to the selected mode by setting the corresponding two bits (Bit DB1 and Bit DB0) to 1.
PAGE 17
AD5663 Synchronous LDAC: The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse. LDAC can be permanently low or pulsed, as shown in Figure 2. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. The LDAC register gives the user full flexibility and control over the hardware LDAC pin.
PAGE 18
AD5663 AD56631 68HC11/68L111 AD5663 to Blackfin® ADSP BF53x Interface PC7 SYNC Figure 32 shows a serial interface between the AD5663 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5663, the setup for the interface is as follows: SCK SCLK MOSI DIN 1ADDITIONAL PINS OMITTED FOR CLARITY.
PAGE 19
AD5663 APPLICATIONS To achieve the optimum performance from the AD5663, thought should be given to the choice of a precision voltage reference. The AD5663 has only one reference input, VREF. The voltage on the reference input is used to supply the positive input to the DAC. Therefore, any error in the reference is reflected in the DAC. When choosing a voltage reference for high accuracy applications, the sources of error are initial accuracy, ppm drift, longterm drift, and output voltage noise.
PAGE 20
AD5663 5V REGULATOR The AD5663 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 37. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. SCLK VIA VOA SCLK 0.
PAGE 21
AD5663 OUTLINE DIMENSIONS INDEX AREA PIN 1 INDICATOR 3.00 BSC SQ 10 1.50 BCS SQ 0.50 BSC 1 (BOTTOM VIEW) 6 0.80 MAX 0.55 TYP 0.80 0.75 0.70 5 0.50 0.40 0.30 1.74 1.64 1.49 0.05 MAX 0.02 NOM SIDE VIEW SEATING PLANE 2.48 2.38 2.23 EXPOSED PAD TOP VIEW 0.30 0.23 0.18 0.20 REF Figure 39. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.
PAGE 22
AD5663 NOTES Rev.
PAGE 23
AD5663 NOTES Rev.