Datasheet

AD5662
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTION
V
DD
1
V
REF
2
V
FB
3
V
OUT
4
GND 8
DIN 7
SCLK 6
SYNC 5
AD5662
TOP VIEW
(Not to Scale)
04777-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. V
DD
should be decoupled to GND.
2 V
REF
Reference Voltage Input.
3 V
FB
Feedback Connection for the Output Amplifier. V
FB
should be connected to V
OUT
for normal operation.
4 V
OUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24
th
clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC.
6 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
7 DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
8 GND Ground Reference Point for All Circuitry on the Part.